udp_rxram_mux Entity Reference

Inheritance diagram for udp_rxram_mux:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
mac_clk	in std_logic
rx_reset	in std_logic
rarp_mode	in std_logic
rarp_addr	in std_logic_vector ( 12 downto 0 )
rarp_data	in std_logic_vector ( 7 downto 0 )
rarp_end_addr	in std_logic_vector ( 12 downto 0 )
rarp_send	in std_logic
rarp_we	in std_logic
pkt_drop_arp	in std_logic
arp_data	in std_logic_vector ( 7 downto 0 )
arp_addr	in std_logic_vector ( 12 downto 0 )
arp_we	in std_logic
arp_end_addr	in std_logic_vector ( 12 downto 0 )
arp_send	in std_logic
pkt_drop_ping	in std_logic
ping_data	in std_logic_vector ( 7 downto 0 )
ping_addr	in std_logic_vector ( 12 downto 0 )
ping_we	in std_logic
ping_end_addr	in std_logic_vector ( 12 downto 0 )
ping_send	in std_logic
pkt_drop_status	in std_logic
status_data	in std_logic_vector ( 7 downto 0 )
status_addr	in std_logic_vector ( 12 downto 0 )
status_we	in std_logic
status_end_addr	in std_logic_vector ( 12 downto 0 )
status_send	in std_logic
my_rx_valid	in std_logic
my_rx_last	in std_logic
rxram_busy	in std_logic
pkt_runt	in std_logic
dia	out std_logic_vector ( 7 downto 0 )
addra	out std_logic_vector ( 12 downto 0 )
wea	out std_logic
rxram_end_addr	out std_logic_vector ( 12 downto 0 )
rxram_send	out std_logic
rxram_dropped	out std_logic

Member Data Documentation

addra

addra out std_logic_vector ( 12 downto 0 )

Port

arp_addr

arp_addr in std_logic_vector ( 12 downto 0 )

Port

arp_data

arp_data in std_logic_vector ( 7 downto 0 )

Port

arp_end_addr

arp_end_addr in std_logic_vector ( 12 downto 0 )

Port

arp_send

arp_send in std_logic

Port

arp_we

arp_we in std_logic

Port

dia

dia out std_logic_vector ( 7 downto 0 )

Port

ieee

ieee

Library

mac_clk

mac_clk in std_logic

Port

my_rx_last

my_rx_last in std_logic

Port

my_rx_valid

my_rx_valid in std_logic

Port

numeric_std

numeric_std

Package

ping_addr

ping_addr in std_logic_vector ( 12 downto 0 )

Port

ping_data

ping_data in std_logic_vector ( 7 downto 0 )

Port

ping_end_addr

ping_end_addr in std_logic_vector ( 12 downto 0 )

Port

ping_send

ping_send in std_logic

Port

ping_we

ping_we in std_logic

Port

pkt_drop_arp

pkt_drop_arp in std_logic

Port

pkt_drop_ping

pkt_drop_ping in std_logic

Port

pkt_drop_status

pkt_drop_status in std_logic

Port

pkt_runt

pkt_runt in std_logic

Port

rarp_addr

rarp_addr in std_logic_vector ( 12 downto 0 )

Port

rarp_data

rarp_data in std_logic_vector ( 7 downto 0 )

Port

rarp_end_addr

rarp_end_addr in std_logic_vector ( 12 downto 0 )

Port

rarp_mode

rarp_mode in std_logic

Port

rarp_send

rarp_send in std_logic

Port

rarp_we

rarp_we in std_logic

Port

rx_reset

rx_reset in std_logic

Port

rxram_busy

rxram_busy in std_logic

Port

rxram_dropped

rxram_dropped out std_logic

Port

rxram_end_addr

rxram_end_addr out std_logic_vector ( 12 downto 0 )

Port

rxram_send

rxram_send out std_logic

Port

status_addr

status_addr in std_logic_vector ( 12 downto 0 )

Port

status_data

status_data in std_logic_vector ( 7 downto 0 )

Port

status_end_addr

status_end_addr in std_logic_vector ( 12 downto 0 )

Port

status_send

status_send in std_logic

Port

status_we

status_we in std_logic

Port

std_logic_1164

std_logic_1164

Package

wea

wea out std_logic

Port

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd