rtl Architecture Reference

Processes
do_ram_ready	( mac_clk )
send_packet	( mac_clk )
build_packet	( mac_clk )
do_ram_ready	( mac_clk )
send_packet	( mac_clk )
build_packet	( mac_clk )
do_ram_ready	( mac_clk )
send_packet	( mac_clk )
build_packet	( mac_clk )

Signals
ram_ready	std_logic
rxram_send_sig	std_logic

Member Function Documentation

build_packet() [1/3]

build_packet (   mac_clk   )

Process

build_packet() [2/3]

build_packet (   mac_clk   )

Process

build_packet() [3/3]

build_packet (   mac_clk   )

Process

do_ram_ready() [1/3]

do_ram_ready (   mac_clk   )

Process

do_ram_ready() [2/3]

do_ram_ready (   mac_clk   )

Process

do_ram_ready() [3/3]

do_ram_ready (   mac_clk   )

Process

send_packet() [1/3]

send_packet (   mac_clk   )

Process

send_packet() [2/3]

send_packet (   mac_clk   )

Process

send_packet() [3/3]

send_packet (   mac_clk   )

Process

Member Data Documentation

ram_ready

ram_ready std_logic

Signal

rxram_send_sig

rxram_send_sig std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_rxram_mux.vhd