udp_DualPortRAM_tx Entity Reference

Inheritance diagram for udp_DualPortRAM_tx:

Entities
v3	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
BUFWIDTH	natural := 0
ADDRWIDTH	natural := 0

Ports
clk	in std_logic
clk125	in std_logic
tx_wea	in std_logic
tx_addra	in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )
tx_addrb	in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )
tx_dia	in std_logic_vector ( 31 downto 0 )
tx_dob	out std_logic_vector ( 7 downto 0 )

Member Data Documentation

ADDRWIDTH

ADDRWIDTH natural := 0

Generic

BUFWIDTH

BUFWIDTH natural := 0

Generic

clk

clk in std_logic

Port

clk125

clk125 in std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

std_logic_1164

std_logic_1164

Package

tx_addra

tx_addra in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )

Port

tx_addrb

tx_addrb in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )

Port

tx_dia

tx_dia in std_logic_vector ( 31 downto 0 )

Port

tx_dob

tx_dob out std_logic_vector ( 7 downto 0 )

Port

tx_wea

tx_wea in std_logic

Port

---

The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd