v3 Architecture Reference

Processes
write	( clk )
read	( clk125 )
write	( clk )
read	( clk125 )
write	( clk )
read	( clk125 )

Types
ram_type	( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) std_logic_vector ( 31 downto 0 )

Signals
ram	ram_type
ram_out	std_logic_vector ( 31 downto 0 )
bytesel	std_logic_vector ( 1 downto 0 )

Member Function Documentation

read() [1/3]

read (   clk125   )

Process

read() [2/3]

read (   clk125   )

Process

read() [3/3]

read (   clk125   )

Process

write() [1/3]

write (   clk   )

Process

write() [2/3]

write (   clk   )

Process

write() [3/3]

write (   clk   )

Process

Member Data Documentation

bytesel

bytesel std_logic_vector ( 1 downto 0 )

Signal

ram

ram ram_type

Signal

ram_out

ram_out std_logic_vector ( 31 downto 0 )

Signal

ram_type

ram_type ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) std_logic_vector ( 31 downto 0 )

Type

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_dualportram_tx.vhd