udp_DualPortRAM_rx Entity Reference

Inheritance diagram for udp_DualPortRAM_rx:

Entities
striped	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
BUFWIDTH	natural := 0
ADDRWIDTH	natural := 0

Ports
clk125	in std_logic
clk	in std_logic
rx_wea	in std_logic
rx_addra	in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )
rx_addrb	in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )
rx_dia	in std_logic_vector ( 7 downto 0 )
rx_dob	out std_logic_vector ( 31 downto 0 )

Member Data Documentation

ADDRWIDTH

ADDRWIDTH natural := 0

Generic

BUFWIDTH

BUFWIDTH natural := 0

Generic

clk

clk in std_logic

Port

clk125

clk125 in std_logic

Port

ieee

ieee

Library

numeric_std

numeric_std

Package

rx_addra

rx_addra in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 1 downto 0 )

Port

rx_addrb

rx_addrb in std_logic_vector ( BUFWIDTH + ADDRWIDTH - 3 downto 0 )

Port

rx_dia

rx_dia in std_logic_vector ( 7 downto 0 )

Port

rx_dob

rx_dob out std_logic_vector ( 31 downto 0 )

Port

rx_wea

rx_wea in std_logic

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_dualportram_rx.vhd