My Project  v0.0.16
Types | Signals | Processes
striped Architecture Reference

Processes

write  ( clk125 )
read  ( clk )
write  ( clk125 )
read  ( clk )
write  ( clk125 )
read  ( clk )

Types

ram_type ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) std_logic_vector ( 7 downto 0 )

Signals

ram1  ram_type
ram2  ram_type
ram3  ram_type
ram4  ram_type

Member Function Documentation

◆ read() [1/3]

read (   clk  
)
Process

◆ read() [2/3]

read (   clk  
)
Process

◆ read() [3/3]

read (   clk  
)
Process

◆ write() [1/3]

write (   clk125  
)
Process

◆ write() [2/3]

write (   clk125  
)
Process

◆ write() [3/3]

write (   clk125  
)
Process

Member Data Documentation

◆ ram1

ram1 ram_type
Signal

◆ ram2

ram2 ram_type
Signal

◆ ram3

ram3 ram_type
Signal

◆ ram4

ram4 ram_type
Signal

◆ ram_type

ram_type ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) std_logic_vector ( 7 downto 0 )
Type

The documentation for this class was generated from the following file: