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My Project
v0.0.16
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Processes | |
| write | ( clk125 ) |
| read | ( clk ) |
| write | ( clk125 ) |
| read | ( clk ) |
| write | ( clk125 ) |
| read | ( clk ) |
Types | |
| ram_type | ( 2 ** ( BUFWIDTH + ADDRWIDTH - 2 ) - 1 downto 0 ) std_logic_vector ( 7 downto 0 ) |
Signals | |
| ram1 | ram_type |
| ram2 | ram_type |
| ram3 | ram_type |
| ram4 | ram_type |
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Process |
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Process |
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Process |
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Process |
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Process |
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Process |
1.8.13