My Project  v0.0.16
Ports | Libraries | Use Clauses
udp_build_arp Entity Reference
Inheritance diagram for udp_build_arp:
Inheritance graph
[legend]

Entities

rtl  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
numeric_std 

Ports

mac_clk   in std_logic
rx_reset   in std_logic
my_rx_data   in std_logic_vector ( 7 downto 0 )
my_rx_valid   in std_logic
my_rx_last   in std_logic
my_rx_error   in std_logic
pkt_drop_arp   in std_logic
My_MAC_addr   in std_logic_vector ( 47 downto 0 )
My_IP_addr   in std_logic_vector ( 31 downto 0 )
arp_data   out std_logic_vector ( 7 downto 0 )
arp_addr   out std_logic_vector ( 12 downto 0 )
arp_we   out std_logic
arp_end_addr   out std_logic_vector ( 12 downto 0 )
arp_send   out std_logic
MAC_addr   in std_logic_vector ( 47 downto 0 )

Member Data Documentation

◆ arp_addr

arp_addr out std_logic_vector ( 12 downto 0 )
Port

◆ arp_data

arp_data out std_logic_vector ( 7 downto 0 )
Port

◆ arp_end_addr

arp_end_addr out std_logic_vector ( 12 downto 0 )
Port

◆ arp_send

arp_send out std_logic
Port

◆ arp_we

arp_we out std_logic
Port

◆ ieee

ieee
Library

◆ MAC_addr

MAC_addr in std_logic_vector ( 47 downto 0 )
Port

◆ mac_clk

mac_clk in std_logic
Port

◆ My_IP_addr

My_IP_addr in std_logic_vector ( 31 downto 0 )
Port

◆ My_MAC_addr

My_MAC_addr in std_logic_vector ( 47 downto 0 )
Port

◆ my_rx_data

my_rx_data in std_logic_vector ( 7 downto 0 )
Port

◆ my_rx_error

my_rx_error in std_logic
Port

◆ my_rx_last

my_rx_last in std_logic
Port

◆ my_rx_valid

my_rx_valid in std_logic
Port

◆ numeric_std

numeric_std
Package

◆ pkt_drop_arp

pkt_drop_arp in std_logic
Port

◆ rx_reset

rx_reset in std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

The documentation for this class was generated from the following file: