My Project  v0.0.16
Signals | Processes
rtl Architecture Reference

Processes

send_packet  ( mac_clk )
address_block  ( mac_clk )
build_packet  ( mac_clk )
next_addr  ( mac_clk )
write_data  ( mac_clk )
send_packet  ( mac_clk )
address_block  ( mac_clk )
build_packet  ( mac_clk )
next_addr  ( mac_clk )
write_data  ( mac_clk )
send_packet  ( mac_clk )
address_block  ( mac_clk )
build_packet  ( mac_clk )
next_addr  ( mac_clk )
write_data  ( mac_clk )

Signals

arp_we_sig  std_logic
set_addr  std_logic
send_buf  std_logic
load_buf  std_logic
buf_to_load  std_logic_vector ( 47 downto 0 )
address  unsigned ( 5 downto 0 )
addr_to_set  unsigned ( 5 downto 0 )

Member Function Documentation

◆ address_block() [1/3]

address_block (   mac_clk  
)
Process

◆ address_block() [2/3]

address_block (   mac_clk  
)
Process

◆ address_block() [3/3]

address_block (   mac_clk  
)
Process

◆ build_packet() [1/3]

build_packet (   mac_clk  
)
Process

◆ build_packet() [2/3]

build_packet (   mac_clk  
)
Process

◆ build_packet() [3/3]

build_packet (   mac_clk  
)
Process

◆ next_addr() [1/3]

next_addr (   mac_clk  
)
Process

◆ next_addr() [2/3]

next_addr (   mac_clk  
)
Process

◆ next_addr() [3/3]

next_addr (   mac_clk  
)
Process

◆ send_packet() [1/3]

send_packet (   mac_clk  
)
Process

◆ send_packet() [2/3]

send_packet (   mac_clk  
)
Process

◆ send_packet() [3/3]

send_packet (   mac_clk  
)
Process

◆ write_data() [1/3]

write_data (   mac_clk  
)
Process

◆ write_data() [2/3]

write_data (   mac_clk  
)
Process

◆ write_data() [3/3]

write_data (   mac_clk  
)
Process

Member Data Documentation

◆ addr_to_set

addr_to_set unsigned ( 5 downto 0 )
Signal

◆ address

address unsigned ( 5 downto 0 )
Signal

◆ arp_we_sig

arp_we_sig std_logic
Signal

◆ buf_to_load

buf_to_load std_logic_vector ( 47 downto 0 )
Signal

◆ load_buf

load_buf std_logic
Signal

◆ send_buf

send_buf std_logic
Signal

◆ set_addr

set_addr std_logic
Signal
The documentation for this class was generated from the following file:
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