udp_rxram_shim Entity Reference

Inheritance diagram for udp_rxram_shim:

Entities
simple	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Generics
BUFWIDTH	natural := 0

Ports
mac_clk	in std_logic
rst_macclk_reg	in std_logic
rxram_end_addr	in std_logic_vector ( 12 downto 0 )
rxram_send	in std_logic
rxram_write_buf	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rxram_req_send	in std_logic
rxram_send_buf	in std_logic_vector ( BUFWIDTH - 1 downto 0 )
rxram_busy	in std_logic
rxram_end_addr_x	out std_logic_vector ( 12 downto 0 )
rxram_send_x	out std_logic
rxram_sent	out std_logic

Member Data Documentation

BUFWIDTH

BUFWIDTH natural := 0

Generic

ieee

ieee

Library

mac_clk

mac_clk in std_logic

Port

numeric_std

numeric_std

Package

rst_macclk_reg

rst_macclk_reg in std_logic

Port

rxram_busy

rxram_busy in std_logic

Port

rxram_end_addr

rxram_end_addr in std_logic_vector ( 12 downto 0 )

Port

rxram_end_addr_x

rxram_end_addr_x out std_logic_vector ( 12 downto 0 )

Port

rxram_req_send

rxram_req_send in std_logic

Port

rxram_send

rxram_send in std_logic

Port

rxram_send_buf

rxram_send_buf in std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

rxram_send_x

rxram_send_x out std_logic

Port

rxram_sent

rxram_sent out std_logic

Port

rxram_write_buf

rxram_write_buf in std_logic_vector ( BUFWIDTH - 1 downto 0 )

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_core/firmware/hdl/udp_rxram_shim.vhd