My Project  v0.0.16
Types | Signals | Processes
simple Architecture Reference

Processes

input_block  ( mac_clk )
output_block  ( mac_clk )
busy_block  ( mac_clk )
input_block  ( mac_clk )
output_block  ( mac_clk )
busy_block  ( mac_clk )
input_block  ( mac_clk )
output_block  ( mac_clk )
busy_block  ( mac_clk )

Types

address_buf ( 2 ** BUFWIDTH - 1 downto 0 ) std_logic_vector ( 12 downto 0 )

Signals

end_address_buf  address_buf
last_busy  std_logic

Member Function Documentation

◆ busy_block() [1/3]

busy_block (   mac_clk  
)
Process

◆ busy_block() [2/3]

busy_block (   mac_clk  
)
Process

◆ busy_block() [3/3]

busy_block (   mac_clk  
)
Process

◆ input_block() [1/3]

input_block (   mac_clk  
)
Process

◆ input_block() [2/3]

input_block (   mac_clk  
)
Process

◆ input_block() [3/3]

input_block (   mac_clk  
)
Process

◆ output_block() [1/3]

output_block (   mac_clk  
)
Process

◆ output_block() [2/3]

output_block (   mac_clk  
)
Process

◆ output_block() [3/3]

output_block (   mac_clk  
)
Process

Member Data Documentation

◆ address_buf

address_buf ( 2 ** BUFWIDTH - 1 downto 0 ) std_logic_vector ( 12 downto 0 )
Type

◆ end_address_buf

end_address_buf address_buf
Signal

◆ last_busy

last_busy std_logic
Signal
The documentation for this class was generated from the following file:
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