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My Project
v0.0.16
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Entities | |
| rtl | architecture |
Libraries | |
| ieee | |
Use Clauses | |
| std_logic_1164 | |
| numeric_std | |
Ports | |
| mac_clk | in std_logic |
| rx_reset | in std_logic |
| my_rx_data | in std_logic_vector ( 7 downto 0 ) |
| my_rx_valid | in std_logic |
| my_rx_last | in std_logic |
| my_rx_error | in std_logic |
| pkt_drop_payload | in std_logic |
| pkt_byteswap | in std_logic |
| outbyte | in std_logic_vector ( 7 downto 0 ) |
| payload_data | out std_logic_vector ( 7 downto 0 ) |
| payload_addr | out std_logic_vector ( 12 downto 0 ) |
| payload_we | out std_logic |
| payload_send | out std_logic |
| do_sum_payload | out std_logic |
| clr_sum_payload | out std_logic |
| int_data_payload | out std_logic_vector ( 7 downto 0 ) |
| int_valid_payload | out std_logic |
| cksum | out std_logic |
| ipbus_in_hdr | out std_logic_vector ( 31 downto 0 ) |
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1.8.13