UDP_master_if Entity Reference

Inheritance diagram for UDP_master_if:

Entities
rtl	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
mac_clk	in std_logic
rst_macclk	in std_logic
mac_rx_data	in std_logic_vector ( 7 DOWNTO 0 )
mac_rx_error	in std_logic
mac_rx_last	in std_logic
mac_rx_valid	in std_logic
rarp_rx_data	in std_logic_vector ( 7 downto 0 )
rarp_rx_last	in std_logic
rarp_rx_valid	in std_logic
Got_IP_addr	out std_logic
FIFO_Full	in std_logic
FIFO_data	out std_logic_vector ( 9 DOWNTO 0 )
FIFO_WriteEn	out std_logic
master_rx_data	out std_logic_vector ( 8 DOWNTO 0 )
master_tx_data	in std_logic_vector ( 8 DOWNTO 0 )
master_tx_err	in std_logic
master_link_down	in std_logic

Member Data Documentation

FIFO_data

FIFO_data out std_logic_vector ( 9 DOWNTO 0 )

Port

FIFO_Full

FIFO_Full in std_logic

Port

FIFO_WriteEn

FIFO_WriteEn out std_logic

Port

Got_IP_addr

Got_IP_addr out std_logic

Port

ieee

ieee

Library

mac_clk

mac_clk in std_logic

Port

mac_rx_data

mac_rx_data in std_logic_vector ( 7 DOWNTO 0 )

Port

mac_rx_error

mac_rx_error in std_logic

Port

mac_rx_last

mac_rx_last in std_logic

Port

mac_rx_valid

mac_rx_valid in std_logic

Port

master_link_down

master_link_down in std_logic

Port

master_rx_data

master_rx_data out std_logic_vector ( 8 DOWNTO 0 )

Port

master_tx_data

master_tx_data in std_logic_vector ( 8 DOWNTO 0 )

Port

master_tx_err

master_tx_err in std_logic

Port

numeric_std

numeric_std

Package

rarp_rx_data

rarp_rx_data in std_logic_vector ( 7 downto 0 )

Port

rarp_rx_last

rarp_rx_last in std_logic

Port

rarp_rx_valid

rarp_rx_valid in std_logic

Port

rst_macclk

rst_macclk in std_logic

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following files:

• components/ipbus_core/firmware/hdl/udp_master_if.vhd
• components/ipbus_core/firmware/hdl/udp_master_if_broken.vhd
• components/ipbus_core/firmware/hdl/udp_master_if_working.vhd