My Project  v0.0.16
Signals | Processes
rtl Architecture Reference

Processes

rx_data_block  ( mac_clk )
tx_data_block  ( mac_clk )
rx_data_block  ( mac_clk )
tx_data_block  ( mac_clk )
rx_data_block  ( mac_clk )
tx_data_block  ( mac_clk )
rx_data_block  ( mac_clk )
tx_data_block  ( mac_clk )

Signals

my_rx_data  std_logic_vector ( 7 DOWNTO 0 )
my_rx_error  std_logic
my_rx_last  std_logic
my_rx_valid  std_logic
Got_IP_addr_sig  std_logic

Member Function Documentation

◆ rx_data_block() [1/4]

rx_data_block (   mac_clk  
)
Process

◆ rx_data_block() [2/4]

rx_data_block (   mac_clk  
)
Process

◆ rx_data_block() [3/4]

rx_data_block (   mac_clk  
)
Process

◆ rx_data_block() [4/4]

rx_data_block (   mac_clk  
)
Process

◆ tx_data_block() [1/4]

tx_data_block (   mac_clk  
)
Process

◆ tx_data_block() [2/4]

tx_data_block (   mac_clk  
)
Process

◆ tx_data_block() [3/4]

tx_data_block (   mac_clk  
)
Process

◆ tx_data_block() [4/4]

tx_data_block (   mac_clk  
)
Process

Member Data Documentation

◆ Got_IP_addr_sig

Got_IP_addr_sig std_logic
Signal

◆ my_rx_data

my_rx_data std_logic_vector ( 7 DOWNTO 0 )
Signal

◆ my_rx_error

my_rx_error std_logic
Signal

◆ my_rx_last

my_rx_last std_logic
Signal

◆ my_rx_valid

my_rx_valid std_logic
Signal
The documentation for this class was generated from the following files:
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