V6_GTXWIZARD_GTX Entity Reference

Inheritance diagram for V6_GTXWIZARD_GTX:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
VCOMPONENTS

Generics
GTX_SIM_GTXRESET_SPEEDUP	integer := 0
GTX_TX_CLK_SOURCE	string := " TXPLL "
GTX_POWER_SAVE	bit_vector := " 0000000000 "

Ports
LOOPBACK_IN	in std_logic_vector ( 2 downto 0 )
RXPOWERDOWN_IN	in std_logic_vector ( 1 downto 0 )
TXPOWERDOWN_IN	in std_logic_vector ( 1 downto 0 )
RXCHARISCOMMA_OUT	out std_logic
RXCHARISK_OUT	out std_logic
RXDISPERR_OUT	out std_logic
RXNOTINTABLE_OUT	out std_logic
RXRUNDISP_OUT	out std_logic
RXCLKCORCNT_OUT	out std_logic_vector ( 2 downto 0 )
RXENMCOMMAALIGN_IN	in std_logic
RXENPCOMMAALIGN_IN	in std_logic
RXDATA_OUT	out std_logic_vector ( 7 downto 0 )
RXRECCLK_OUT	out std_logic
RXRESET_IN	in std_logic
RXUSRCLK2_IN	in std_logic
RXELECIDLE_OUT	out std_logic
RXN_IN	in std_logic
RXP_IN	in std_logic
RXBUFRESET_IN	in std_logic
RXBUFSTATUS_OUT	out std_logic_vector ( 2 downto 0 )
GTXRXRESET_IN	in std_logic
MGTREFCLKRX_IN	in std_logic_vector ( 1 downto 0 )
PLLRXRESET_IN	in std_logic
RXPLLLKDET_OUT	out std_logic
RXRESETDONE_OUT	out std_logic
TXCHARDISPMODE_IN	in std_logic
TXCHARDISPVAL_IN	in std_logic
TXCHARISK_IN	in std_logic
GTXTEST_IN	in std_logic_vector ( 12 downto 0 )
TXDATA_IN	in std_logic_vector ( 7 downto 0 )
TXOUTCLK_OUT	out std_logic
TXRESET_IN	in std_logic
TXUSRCLK2_IN	in std_logic
TXN_OUT	out std_logic
TXP_OUT	out std_logic
TXBUFSTATUS_OUT	out std_logic_vector ( 1 downto 0 )
GTXTXRESET_IN	in std_logic
MGTREFCLKTX_IN	in std_logic_vector ( 1 downto 0 )
PLLTXRESET_IN	in std_logic
TXPLLLKDET_OUT	out std_logic
TXRESETDONE_OUT	out std_logic

Member Data Documentation

GTX_POWER_SAVE

GTX_POWER_SAVE bit_vector := " 0000000000 "

Generic

GTX_SIM_GTXRESET_SPEEDUP

GTX_SIM_GTXRESET_SPEEDUP integer := 0

Generic

GTX_TX_CLK_SOURCE

GTX_TX_CLK_SOURCE string := " TXPLL "

Generic

GTXRXRESET_IN

GTXRXRESET_IN in std_logic

Port

GTXTEST_IN

GTXTEST_IN in std_logic_vector ( 12 downto 0 )

Port

GTXTXRESET_IN

GTXTXRESET_IN in std_logic

Port

ieee

ieee

Library

LOOPBACK_IN

LOOPBACK_IN in std_logic_vector ( 2 downto 0 )

Port

MGTREFCLKRX_IN

MGTREFCLKRX_IN in std_logic_vector ( 1 downto 0 )

Port

MGTREFCLKTX_IN

MGTREFCLKTX_IN in std_logic_vector ( 1 downto 0 )

Port

numeric_std

numeric_std

Package

PLLRXRESET_IN

PLLRXRESET_IN in std_logic

Port

PLLTXRESET_IN

PLLTXRESET_IN in std_logic

Port

RXBUFRESET_IN

RXBUFRESET_IN in std_logic

Port

RXBUFSTATUS_OUT

RXBUFSTATUS_OUT out std_logic_vector ( 2 downto 0 )

Port

RXCHARISCOMMA_OUT

RXCHARISCOMMA_OUT out std_logic

Port

RXCHARISK_OUT

RXCHARISK_OUT out std_logic

Port

RXCLKCORCNT_OUT

RXCLKCORCNT_OUT out std_logic_vector ( 2 downto 0 )

Port

RXDATA_OUT

RXDATA_OUT out std_logic_vector ( 7 downto 0 )

Port

RXDISPERR_OUT

RXDISPERR_OUT out std_logic

Port

RXELECIDLE_OUT

RXELECIDLE_OUT out std_logic

Port

RXENMCOMMAALIGN_IN

RXENMCOMMAALIGN_IN in std_logic

Port

RXENPCOMMAALIGN_IN

RXENPCOMMAALIGN_IN in std_logic

Port

RXN_IN

RXN_IN in std_logic

Port

RXNOTINTABLE_OUT

RXNOTINTABLE_OUT out std_logic

Port

RXP_IN

RXP_IN in std_logic

Port

RXPLLLKDET_OUT

RXPLLLKDET_OUT out std_logic

Port

RXPOWERDOWN_IN

RXPOWERDOWN_IN in std_logic_vector ( 1 downto 0 )

Port

RXRECCLK_OUT

RXRECCLK_OUT out std_logic

Port

RXRESET_IN

RXRESET_IN in std_logic

Port

RXRESETDONE_OUT

RXRESETDONE_OUT out std_logic

Port

RXRUNDISP_OUT

RXRUNDISP_OUT out std_logic

Port

RXUSRCLK2_IN

RXUSRCLK2_IN in std_logic

Port

std_logic_1164

std_logic_1164

Package

TXBUFSTATUS_OUT

TXBUFSTATUS_OUT out std_logic_vector ( 1 downto 0 )

Port

TXCHARDISPMODE_IN

TXCHARDISPMODE_IN in std_logic

Port

TXCHARDISPVAL_IN

TXCHARDISPVAL_IN in std_logic

Port

TXCHARISK_IN

TXCHARISK_IN in std_logic

Port

TXDATA_IN

TXDATA_IN in std_logic_vector ( 7 downto 0 )

Port

TXN_OUT

TXN_OUT out std_logic

Port

TXOUTCLK_OUT

TXOUTCLK_OUT out std_logic

Port

TXP_OUT

TXP_OUT out std_logic

Port

TXPLLLKDET_OUT

TXPLLLKDET_OUT out std_logic

Port

TXPOWERDOWN_IN

TXPOWERDOWN_IN in std_logic_vector ( 1 downto 0 )

Port

TXRESET_IN

TXRESET_IN in std_logic

Port

TXRESETDONE_OUT

TXRESETDONE_OUT out std_logic

Port

TXUSRCLK2_IN

TXUSRCLK2_IN in std_logic

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v6_emac_v2_3_basex/v6_gtxwizard_gtx.vhd