RTL Architecture Reference

Signals
tied_to_ground_i	std_logic
tied_to_ground_vec_i	std_logic_vector ( 63 downto 0 )
tied_to_vcc_i	std_logic
rxdata_i	std_logic_vector ( 31 downto 0 )
rxchariscomma_float_i	std_logic_vector ( 2 downto 0 )
rxcharisk_float_i	std_logic_vector ( 2 downto 0 )
rxdisperr_float_i	std_logic_vector ( 2 downto 0 )
rxnotintable_float_i	std_logic_vector ( 2 downto 0 )
rxrundisp_float_i	std_logic_vector ( 2 downto 0 )
txdata_i	std_logic_vector ( 31 downto 0 )
txkerr_float_i	std_logic_vector ( 2 downto 0 )
txrundisp_float_i	std_logic_vector ( 2 downto 0 )

Instantiations
gtxe1_i	gtxe1
gtxe1_i	gtxe1

Member Data Documentation

gtxe1_i [1/2]

gtxe1_i gtxe1

Instantiation

gtxe1_i [2/2]

gtxe1_i gtxe1

Instantiation

rxchariscomma_float_i

rxchariscomma_float_i std_logic_vector ( 2 downto 0 )

Signal

rxcharisk_float_i

rxcharisk_float_i std_logic_vector ( 2 downto 0 )

Signal

rxdata_i

rxdata_i std_logic_vector ( 31 downto 0 )

Signal

rxdisperr_float_i

rxdisperr_float_i std_logic_vector ( 2 downto 0 )

Signal

rxnotintable_float_i

rxnotintable_float_i std_logic_vector ( 2 downto 0 )

Signal

rxrundisp_float_i

rxrundisp_float_i std_logic_vector ( 2 downto 0 )

Signal

tied_to_ground_i

tied_to_ground_i std_logic

Signal

tied_to_ground_vec_i

tied_to_ground_vec_i std_logic_vector ( 63 downto 0 )

Signal

tied_to_vcc_i

tied_to_vcc_i std_logic

Signal

txdata_i

txdata_i std_logic_vector ( 31 downto 0 )

Signal

txkerr_float_i

txkerr_float_i std_logic_vector ( 2 downto 0 )

Signal

txrundisp_float_i

txrundisp_float_i std_logic_vector ( 2 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/gen_hdl/v6_emac_v2_3_basex/v6_gtxwizard_gtx.vhd