address_decoder Entity Reference

Inheritance diagram for address_decoder:

Collaboration diagram for address_decoder:

Entities
IMP	architecture

Libraries
IEEE
axi_lite_ipif_v3_0_4

Use Clauses
std_logic_1164
numeric_std
ipif_pkg	Package <ipif_pkg>

Generics
C_BUS_AWIDTH	integer := 32
C_S_AXI_MIN_SIZE	std_logic_vector ( 0 to 31 ) := X " 000001FF "
C_ARD_ADDR_RANGE_ARRAY	SLV64_ARRAY_TYPE := ( X " 0000_0000_1000_0000 " , X " 0000_0000_1000_01FF " , X " 0000_0000_1000_0200 " , X " 0000_0000_1000_02FF " )
C_ARD_NUM_CE_ARRAY	INTEGER_ARRAY_TYPE := ( 8 , 1 )
C_FAMILY	string := " virtex6 "

Ports
Bus_clk	in std_logic
Bus_rst	in std_logic
Address_In_Erly	in std_logic_vector ( 0 to C_BUS_AWIDTH - 1 )
Address_Valid_Erly	in std_logic
Bus_RNW	in std_logic
Bus_RNW_Erly	in std_logic
CS_CE_ld_enable	in std_logic
Clear_CS_CE_Reg	in std_logic
RW_CE_ld_enable	in std_logic
CS_for_gaps	out std_logic
CS_Out	out std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )
RdCE_Out	out std_logic_vector ( 0 to calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 )
WrCE_Out	out std_logic_vector ( 0 to calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 )

Member Data Documentation

Address_In_Erly

Address_In_Erly in std_logic_vector ( 0 to C_BUS_AWIDTH - 1 )

Port

Address_Valid_Erly

Address_Valid_Erly in std_logic

Port

axi_lite_ipif_v3_0_4

axi_lite_ipif_v3_0_4

Library

Bus_clk

Bus_clk in std_logic

Port

Bus_RNW

Bus_RNW in std_logic

Port

Bus_RNW_Erly

Bus_RNW_Erly in std_logic

Port

Bus_rst

Bus_rst in std_logic

Port

C_ARD_ADDR_RANGE_ARRAY

C_ARD_ADDR_RANGE_ARRAY SLV64_ARRAY_TYPE := ( X " 0000_0000_1000_0000 " , X " 0000_0000_1000_01FF " , X " 0000_0000_1000_0200 " , X " 0000_0000_1000_02FF " )

Generic

C_ARD_NUM_CE_ARRAY

C_ARD_NUM_CE_ARRAY INTEGER_ARRAY_TYPE := ( 8 , 1 )

Generic

C_BUS_AWIDTH

C_BUS_AWIDTH integer := 32

Generic

C_FAMILY

C_FAMILY string := " virtex6 "

Generic

C_S_AXI_MIN_SIZE

C_S_AXI_MIN_SIZE std_logic_vector ( 0 to 31 ) := X " 000001FF "

Generic

Clear_CS_CE_Reg

Clear_CS_CE_Reg in std_logic

Port

CS_CE_ld_enable

CS_CE_ld_enable in std_logic

Port

CS_for_gaps

CS_for_gaps out std_logic

Port

CS_Out

CS_Out out std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )

Port

IEEE

IEEE

Library

ipif_pkg

ipif_pkg

Package

numeric_std

numeric_std

Package

RdCE_Out

RdCE_Out out std_logic_vector ( 0 to calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 )

Port

RW_CE_ld_enable

RW_CE_ld_enable in std_logic

Port

std_logic_1164

std_logic_1164

Package

WrCE_Out

WrCE_Out out std_logic_vector ( 0 to calc_num_ce ( C_ARD_NUM_CE_ARRAY ) - 1 )

Port

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd