IMP Architecture Reference

Functions
short_addr_array_type	slv64_2_slv_awidth ( slv64_addr_array: in SLV64_ARRAY_TYPE , awidth: in integer )
integer	Addr_Bits ( x: in std_logic_vector( 0 to C_BUS_AWIDTH- 1) , y: in std_logic_vector( 0 to C_BUS_AWIDTH- 1) )
decode_bit_array_type	Get_Addr_Bits ( baseaddrs: in short_addr_array_type )
integer	needed_addr_bits ( ce_array: in INTEGER_ARRAY_TYPE )
std_logic_vector	calc_high_address ( high_address: in short_addr_array_type , index: in integer )

Processes
BKEND_CS_REG	( Bus_Clk )
RNW_REG_P	( Bus_Clk )
BKEND_RDCE_REG	( Bus_Clk )

Constants
ARD_ADDR_RANGE_ARRAY	short_addr_array_type := slv64_2_slv_awidth ( C_ARD_ADDR_RANGE_ARRAY , C_BUS_AWIDTH )
NUM_BASE_ADDRS	integer := ( C_ARD_ADDR_RANGE_ARRAY ' length ) / 2
DECODE_BITS	decode_bit_array_type := Get_Addr_Bits ( ARD_ADDR_RANGE_ARRAY )
NUM_CE_SIGNALS	integer := calc_num_ce ( C_ARD_NUM_CE_ARRAY )
NUM_S_H_ADDR_BITS	integer := needed_addr_bits ( C_ARD_NUM_CE_ARRAY )
CE_INDEX_START	integer := calc_start_ce_index ( C_ARD_NUM_CE_ARRAY , bar_index )
CE_ADDR_SIZE	Integer range 0 to 15 := clog2 ( C_ARD_NUM_CE_ARRAY ( bar_index ) )
OFFSET	integer := 2
BASE_ADDR_x	std_logic_vector ( 0 to C_BUS_AWIDTH - 1 ) := ARD_ADDR_RANGE_ARRAY ( bar_index* 2 + 1 )
HIGH_ADDR_X	std_logic_vector ( 0 to C_BUS_AWIDTH - 1 ) := calc_high_address ( ARD_ADDR_RANGE_ARRAY , bar_index )
BAR	std_logic_vector ( 0 to CE_ADDR_SIZE - 1 ) := std_logic_vector ( to_unsigned ( j , CE_ADDR_SIZE ) )

Types
decode_bit_array_type	( natural range 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 ) integer
short_addr_array_type	( natural range 0 to C_ARD_ADDR_RANGE_ARRAY ' LENGTH- 1 ) std_logic_vector ( 0 to C_BUS_AWIDTH - 1 )

Signals
pselect_hit_i	std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )
cs_out_i	std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )
ce_expnd_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )
rdce_out_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )
wrce_out_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )
ce_out_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )
cs_ce_clr	std_logic
addr_out_s_h	std_logic_vector ( 0 to NUM_S_H_ADDR_BITS - 1 )
Bus_RNW_reg	std_logic
rdce_expnd_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )
wrce_expnd_i	std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Attributes
DowngradeIPIdentifiedWarnings	string
DowngradeIPIdentifiedWarnings	imp : architecture is " yes "

Instantiations
mem_select_i	pselect_f <Entity pselect_f>
ce_i	pselect_f <Entity pselect_f>

Member Function Documentation

Addr_Bits()

integer Addr_Bits (   x in std_logic_vector( 0 to C_BUS_AWIDTH - 1 ) ,   y in std_logic_vector( 0 to C_BUS_AWIDTH - 1 )   )

Function

BKEND_CS_REG()

BKEND_CS_REG

(

Bus_Clk

)

BKEND_RDCE_REG()

BKEND_RDCE_REG (   Bus_Clk   )

Process

calc_high_address()

std_logic_vector calc_high_address (   high_address in short_addr_array_type ,   index in integer   )

Function

Get_Addr_Bits()

decode_bit_array_type Get_Addr_Bits (   baseaddrs in short_addr_array_type   )

Function

needed_addr_bits()

integer needed_addr_bits (   ce_array in INTEGER_ARRAY_TYPE   )

Function

RNW_REG_P()

RNW_REG_P

(

Bus_Clk

)

slv64_2_slv_awidth()

short_addr_array_type slv64_2_slv_awidth (   slv64_addr_array in SLV64_ARRAY_TYPE ,   awidth in integer   )

Function

Member Data Documentation

addr_out_s_h

addr_out_s_h std_logic_vector ( 0 to NUM_S_H_ADDR_BITS - 1 )

Signal

ARD_ADDR_RANGE_ARRAY

ARD_ADDR_RANGE_ARRAY short_addr_array_type := slv64_2_slv_awidth ( C_ARD_ADDR_RANGE_ARRAY , C_BUS_AWIDTH )

Constant

BAR

BAR std_logic_vector ( 0 to CE_ADDR_SIZE - 1 ) := std_logic_vector ( to_unsigned ( j , CE_ADDR_SIZE ) )

Constant

BASE_ADDR_x

BASE_ADDR_x std_logic_vector ( 0 to C_BUS_AWIDTH - 1 ) := ARD_ADDR_RANGE_ARRAY ( bar_index* 2 + 1 )

Constant

Bus_RNW_reg

Bus_RNW_reg std_logic

Signal

CE_ADDR_SIZE

CE_ADDR_SIZE Integer range 0 to 15 := clog2 ( C_ARD_NUM_CE_ARRAY ( bar_index ) )

Constant

ce_expnd_i

ce_expnd_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

ce_i

ce_i pselect_f

Instantiation

CE_INDEX_START

CE_INDEX_START integer := calc_start_ce_index ( C_ARD_NUM_CE_ARRAY , bar_index )

Constant

ce_out_i

ce_out_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

cs_ce_clr

cs_ce_clr std_logic

Signal

cs_out_i

cs_out_i std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )

Signal

decode_bit_array_type

decode_bit_array_type ( natural range 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 ) integer

Type

DECODE_BITS

DECODE_BITS decode_bit_array_type := Get_Addr_Bits ( ARD_ADDR_RANGE_ARRAY )

Constant

DowngradeIPIdentifiedWarnings [1/2]

DowngradeIPIdentifiedWarnings string

Attribute

DowngradeIPIdentifiedWarnings [2/2]

DowngradeIPIdentifiedWarnings imp : architecture is " yes "

Attribute

HIGH_ADDR_X

HIGH_ADDR_X std_logic_vector ( 0 to C_BUS_AWIDTH - 1 ) := calc_high_address ( ARD_ADDR_RANGE_ARRAY , bar_index )

Constant

mem_select_i

mem_select_i pselect_f

Instantiation

NUM_BASE_ADDRS

NUM_BASE_ADDRS integer := ( C_ARD_ADDR_RANGE_ARRAY ' length ) / 2

Constant

NUM_CE_SIGNALS

NUM_CE_SIGNALS integer := calc_num_ce ( C_ARD_NUM_CE_ARRAY )

Constant

NUM_S_H_ADDR_BITS

NUM_S_H_ADDR_BITS integer := needed_addr_bits ( C_ARD_NUM_CE_ARRAY )

Constant

OFFSET

OFFSET integer := 2

Constant

pselect_hit_i

pselect_hit_i std_logic_vector ( 0 to ( ( C_ARD_ADDR_RANGE_ARRAY ' LENGTH ) / 2 ) - 1 )

Signal

rdce_expnd_i

rdce_expnd_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

rdce_out_i

rdce_out_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

short_addr_array_type

short_addr_array_type ( natural range 0 to C_ARD_ADDR_RANGE_ARRAY ' LENGTH- 1 ) std_logic_vector ( 0 to C_BUS_AWIDTH - 1 )

Type

wrce_expnd_i

wrce_expnd_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

wrce_out_i

wrce_out_i std_logic_vector ( 0 to NUM_CE_SIGNALS - 1 )

Signal

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The documentation for this class was generated from the following file:

• IP/temac_gbe_v9_0_gmii/hdl/axi_lite_ipif_v3_0_vh_rfs.vhd