My Project  v0.0.16
Generics | Ports | Libraries | Use Clauses
algo_pointer Entity Reference
Inheritance diagram for algo_pointer:
Inheritance graph
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Entities

rtl  architecture
 

Libraries

IEEE 
UNISIM 

Use Clauses

STD_LOGIC_1164 
numeric_std 
vcomponents 

Generics

ADDR_WIDTH  natural := 16

Ports

clk40   in STD_LOGIC
clk200   in STD_LOGIC
loadin   in STD_LOGIC
zero   in STD_LOGIC
spin   in STD_LOGIC
sync40   out std_logic := ' 0 '
spin40   out std_logic := ' 0 '
sync200   out std_logic := ' 0 '
max_val   in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
tob_delay_value   in std_logic_vector ( 4 downto 0 )
pointer   out std_logic_vector ( ADDR_WIDTH - 1 downto 0 )

Member Data Documentation

◆ ADDR_WIDTH

ADDR_WIDTH natural := 16
Generic

◆ clk200

clk200 in STD_LOGIC
Port

◆ clk40

clk40 in STD_LOGIC
Port

◆ IEEE

IEEE
Library

◆ loadin

loadin in STD_LOGIC
Port

◆ max_val

max_val in std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
Port

◆ numeric_std

numeric_std
Package

◆ pointer

pointer out std_logic_vector ( ADDR_WIDTH - 1 downto 0 )
Port

◆ spin

spin in STD_LOGIC
Port

◆ spin40

spin40 out std_logic := ' 0 '
Port

◆ STD_LOGIC_1164

STD_LOGIC_1164
Package

◆ sync200

sync200 out std_logic := ' 0 '
Port

◆ sync40

sync40 out std_logic := ' 0 '
Port

◆ tob_delay_value

tob_delay_value in std_logic_vector ( 4 downto 0 )
Port

◆ UNISIM

UNISIM
Library

◆ vcomponents

vcomponents
Package

◆ zero

zero in STD_LOGIC
Port

The documentation for this class was generated from the following file: