rtl Architecture Reference

Processes
metastab	( clk40 , ptr )
mastertob	( clk200 , loadin )
masteralgo	( clk40 , ptr )

Signals
max_pointer_val	natural range 0 to 2 ** ADDR_WIDTH - 1
ptr	natural range 0 to 2 ** ADDR_WIDTH - 1 := 0
sync_int	std_logic := ' 0 '
sync200int	std_logic := ' 0 '
spin_q	std_logic := ' 0 '
zero_q	std_logic := ' 0 '
delayline	std_logic_vector ( 4 downto 0 )

Instantiations
fine_delay	srlc32e

Member Function Documentation

masteralgo()

masteralgo (   clk40 ,   ptr   )

Process

mastertob()

mastertob (   clk200 ,   loadin   )

Process

metastab()

metastab (   clk40 ,   ptr   )

Process

Member Data Documentation

delayline

delayline std_logic_vector ( 4 downto 0 )

Signal

fine_delay

fine_delay srlc32e

Instantiation

max_pointer_val

max_pointer_val natural range 0 to 2 ** ADDR_WIDTH - 1

Signal

ptr

ptr natural range 0 to 2 ** ADDR_WIDTH - 1 := 0

Signal

spin_q

spin_q std_logic := ' 0 '

Signal

sync200int

sync200int std_logic := ' 0 '

Signal

sync_int

sync_int std_logic := ' 0 '

Signal

zero_q

zero_q std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/algo_pointer.vhd