asymmetric_ram Entity Reference

Inheritance diagram for asymmetric_ram:

Entities
behavioral	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith

Generics
WIDTHA	integer := 16
SIZEA	integer := 1024
ADDRWIDTHA	integer := 10
WIDTHB	integer := 64
SIZEB	integer := 256
ADDRWIDTHB	integer := 8

Ports
clkA	in std_logic
clkB	in std_logic
enA	in std_logic
enB	in std_logic
weA	in std_logic
weB	in std_logic
addrA	in std_logic_vector ( ADDRWIDTHA - 1 downto 0 )
addrB	in std_logic_vector ( ADDRWIDTHB - 1 downto 0 )
diA	in std_logic_vector ( WIDTHA - 1 downto 0 )
diB	in std_logic_vector ( WIDTHB - 1 downto 0 )
doA	out std_logic_vector ( WIDTHA - 1 downto 0 )
doB	out std_logic_vector ( WIDTHB - 1 downto 0 )

Member Data Documentation

addrA

addrA in std_logic_vector ( ADDRWIDTHA - 1 downto 0 )

Port

addrB

addrB in std_logic_vector ( ADDRWIDTHB - 1 downto 0 )

Port

ADDRWIDTHA

ADDRWIDTHA integer := 10

Generic

ADDRWIDTHB

ADDRWIDTHB integer := 8

Generic

clkA

clkA in std_logic

Port

clkB

clkB in std_logic

Port

diA

diA in std_logic_vector ( WIDTHA - 1 downto 0 )

Port

diB

diB in std_logic_vector ( WIDTHB - 1 downto 0 )

Port

doA

doA out std_logic_vector ( WIDTHA - 1 downto 0 )

Port

doB

doB out std_logic_vector ( WIDTHB - 1 downto 0 )

Port

enA

enA in std_logic

Port

enB

enB in std_logic

Port

ieee

ieee

Library

SIZEA

SIZEA integer := 1024

Generic

SIZEB

SIZEB integer := 256

Generic

std_logic_1164

std_logic_1164

Package

std_logic_arith

std_logic_arith

Package

std_logic_unsigned

std_logic_unsigned

Package

weA

weA in std_logic

Port

weB

weB in std_logic

Port

WIDTHA

WIDTHA integer := 16

Generic

WIDTHB

WIDTHB integer := 64

Generic

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/asymmetric_ram.vhd