behavioral Architecture Reference

Functions
INTEGER	max ( L: in INTEGER , R: in INTEGER )
INTEGER	min ( L: in INTEGER , R: in INTEGER )
natural	log2 ( val: in INTEGER )

Processes
PROCESS_481	( clkA )
PROCESS_482	( clkB )

Constants
minWIDTH	integer := min ( WIDTHA , WIDTHB )
maxWIDTH	integer := max ( WIDTHA , WIDTHB )
maxSIZE	integer := max ( SIZEA , SIZEB )
RATIO	integer := maxWIDTH / minWIDTH

Types
ramType	( 0 to maxSIZE - 1 ) std_logic_vector ( minWIDTH - 1 downto 0 )

Signals
readA	std_logic_vector ( WIDTHA - 1 downto 0 ) := ( others = > ' 0 ' )
readB	std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )
regA	std_logic_vector ( WIDTHA - 1 downto 0 ) := ( others = > ' 0 ' )
regB	std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )

Shared Variables
ram	shared ramType := := ( others = > ( others = > ' 0 ' ) )

Member Function Documentation

log2()

natural log2 (   val in INTEGER   )

Function

max()

INTEGER max (   L in INTEGER ,   R in INTEGER   )

Function

min()

INTEGER min (   L in INTEGER ,   R in INTEGER   )

Function

PROCESS_481()

PROCESS_481 (   clkA   )

Process

PROCESS_482()

PROCESS_482 (   clkB   )

Process

Member Data Documentation

maxSIZE

maxSIZE integer := max ( SIZEA , SIZEB )

Constant

maxWIDTH

maxWIDTH integer := max ( WIDTHA , WIDTHB )

Constant

minWIDTH

minWIDTH integer := min ( WIDTHA , WIDTHB )

Constant

ram

ram shared ramType := := ( others = > ( others = > ' 0 ' ) )

Shared Variable

ramType

ramType ( 0 to maxSIZE - 1 ) std_logic_vector ( minWIDTH - 1 downto 0 )

Type

RATIO

RATIO integer := maxWIDTH / minWIDTH

Constant

readA

readA std_logic_vector ( WIDTHA - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

readB

readB std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

regA

regA std_logic_vector ( WIDTHA - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

regB

regB std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/asymmetric_ram.vhd