struct Architecture Reference

Constants
bignull	std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )

Types
bigbus	( 2 downto 0 ) std_logic_vector ( WIDTHA - 1 downto 0 )

Signals
ReMapAddrA	std_logic_vector ( ADDRWIDTHA - 3 downto 0 )
ena_decoder	std_logic_vector ( 2 downto 0 )
address	integer range 0 to 2
Abus	bigbus

Instantiations
infered_ram	asymmetric_ram <Entity asymmetric_ram>

Member Data Documentation

Abus

Abus bigbus

Signal

address

address integer range 0 to 2

Signal

bigbus

bigbus ( 2 downto 0 ) std_logic_vector ( WIDTHA - 1 downto 0 )

Type

bignull

bignull std_logic_vector ( WIDTHB - 1 downto 0 ) := ( others = > ' 0 ' )

Constant

ena_decoder

ena_decoder std_logic_vector ( 2 downto 0 )

Signal

infered_ram

infered_ram asymmetric_ram

Instantiation

ReMapAddrA

ReMapAddrA std_logic_vector ( ADDRWIDTHA - 3 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/asymmetric_ram_tt.vhd