big_fifo_72 Entity Reference

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
ipbus_reg_types	Package <ipbus_reg_types>
VComponents

Generics
N_FIFO	positive

Ports
clk	in std_logic
rst	in std_logic
d	in std_logic_vector ( 71 downto 0 )
wen	in std_logic
full	out std_logic
empty	out std_logic
ctr	out std_logic_vector ( 17 downto 0 )
ren	in std_logic
q	out std_logic_vector ( 71 downto 0 )
valid	out std_logic

Member Data Documentation

clk

clk in std_logic

Port

ctr

ctr out std_logic_vector ( 17 downto 0 )

Port

d

d in std_logic_vector ( 71 downto 0 )

Port

empty

empty out std_logic

Port

full

full out std_logic

Port

ieee

ieee

Library

ipbus_reg_types

ipbus_reg_types

Package

N_FIFO

N_FIFO positive

Generic

numeric_std

numeric_std

Package

q

q out std_logic_vector ( 71 downto 0 )

Port

ren

ren in std_logic

Port

rst

rst in std_logic

Port

std_logic_1164

std_logic_1164

Package

unisim

unisim

Library

valid

valid out std_logic

Port

VComponents

VComponents

Package

wen

wen in std_logic

Port

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/big_fifo_72.vhd