rtl Architecture Reference

Processes
PROCESS_312	( clk )
PROCESS_313	( clk )
PROCESS_872	( clk )
PROCESS_873	( clk )

Types
fifo_d_t	( N_FIFO downto 0 ) std_logic_vector ( 71 downto 0 )

Signals
en	std_logic_vector ( N_FIFO downto 0 )
ifull	std_logic_vector ( N_FIFO - 1 downto 0 )
iempty	std_logic_vector ( N_FIFO - 1 downto 0 )
rsti	std_logic
warn_i	std_logic
fifo_rst	std_logic
fifo_d	fifo_d_t
rst_ctr	unsigned ( 3 downto 0 )
ctri	unsigned ( 17 downto 0 )

Instantiations
fifo	fifo36e1
fifo	fifo36e1

Member Function Documentation

PROCESS_312()

PROCESS_312 (   clk   )

Process

PROCESS_313()

PROCESS_313

(

clk

)

PROCESS_872()

PROCESS_872 (   clk   )

Process

PROCESS_873()

PROCESS_873

(

clk

)

Member Data Documentation

ctri

ctri unsigned ( 17 downto 0 )

Signal

en

en std_logic_vector ( N_FIFO downto 0 )

Signal

fifo [1/2]

fifo fifo36e1

Instantiation

fifo [2/2]

fifo fifo36e1

Instantiation

fifo_d

fifo_d fifo_d_t

Signal

fifo_d_t

fifo_d_t ( N_FIFO downto 0 ) std_logic_vector ( 71 downto 0 )

Type

fifo_rst

fifo_rst std_logic

Signal

iempty

iempty std_logic_vector ( N_FIFO - 1 downto 0 )

Signal

ifull

ifull std_logic_vector ( N_FIFO - 1 downto 0 )

Signal

rst_ctr

rst_ctr unsigned ( 3 downto 0 )

Signal

rsti

rsti std_logic

Signal

warn_i

warn_i std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/big_fifo_72.vhd