cdr2a_b_clk Entity Reference

Inheritance diagram for cdr2a_b_clk:

Entities
behavioral	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
std_logic_misc
vcomponents
all

Generics
pll_locked_delay	integer := 200

Ports
cdrclk_in	in std_logic
cdrdata_in	in std_logic
cdrlock_in	in std_logic
cdrlock_out	out std_logic
div_nrst	out std_logic
ttc_clock	out std_logic
Achannel	out std_logic
Bchannel	out std_logic
ttc_frame_reset	out std_logic
ttc_strobe	out std_logic

Member Data Documentation

all

all

Package

Achannel

Achannel out std_logic

Port

Bchannel

Bchannel out std_logic

Port

cdrclk_in

cdrclk_in in std_logic

Port

cdrdata_in

cdrdata_in in std_logic

Port

cdrlock_in

cdrlock_in in std_logic

Port

cdrlock_out

cdrlock_out out std_logic

Port

div_nrst

div_nrst out std_logic

Port

ieee

ieee

Library

pll_locked_delay

pll_locked_delay integer := 200

Generic

std_logic_1164

std_logic_1164

Package

std_logic_arith

std_logic_arith

Package

std_logic_misc

std_logic_misc

Package

std_logic_unsigned

std_logic_unsigned

Package

ttc_clock

ttc_clock out std_logic

Port

ttc_frame_reset

ttc_frame_reset out std_logic

Port

ttc_strobe

ttc_strobe out std_logic

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

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The documentation for this class was generated from the following file:

• common/TTC_FMC/hdl/decoder_release_1.1/cdr2a_b_clk.vhd