behavioral Architecture Reference

Processes
delay_after_lock	( cdrclk , cdrlock_in )
PROCESS_28	( cdrclk , cdr_lock )
PROCESS_29	( cdrclk , cdr_lock )
PROCESS_30	( cdrclk )

Signals
cdrclk	std_logic := ' 0 '
cdr_lock	std_logic := ' 0 '
cdrdata_q	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
div8	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
toggle_cnt	std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )
toggle_channel	std_logic := ' 1 '
a_channel_time_domain	std_logic := ' 1 '
l1a	std_logic := ' 0 '
strng_length	std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )
div_rst_cnt	std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )
ttc_str	std_logic := ' 0 '
ttcclk	std_logic := ' 0 '
sr	std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )
rec_cntr	std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )
rec_frame	std_logic := ' 0 '
fmt	std_logic := ' 0 '

Attributes
keep	string

Member Function Documentation

delay_after_lock()

delay_after_lock (   cdrclk ,   cdrlock_in   )

Process

PROCESS_28()

PROCESS_28 (   cdrclk ,   cdr_lock   )

Process

PROCESS_29()

PROCESS_29 (   cdrclk ,   cdr_lock   )

Process

PROCESS_30()

PROCESS_30 (   cdrclk   )

Process

Member Data Documentation

a_channel_time_domain

a_channel_time_domain std_logic := ' 1 '

Signal

cdr_lock

cdr_lock std_logic := ' 0 '

Signal

cdrclk

cdrclk std_logic := ' 0 '

Signal

cdrdata_q

cdrdata_q std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

div8

div8 std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

div_rst_cnt

div_rst_cnt std_logic_vector ( 4 downto 0 ) := ( others = > ' 0 ' )

Signal

fmt

fmt std_logic := ' 0 '

Signal

keep

keep string

Attribute

l1a

l1a std_logic := ' 0 '

Signal

rec_cntr

rec_cntr std_logic_vector ( 5 downto 0 ) := ( others = > ' 0 ' )

Signal

rec_frame

rec_frame std_logic := ' 0 '

Signal

sr

sr std_logic_vector ( 12 downto 0 ) := ( others = > ' 0 ' )

Signal

strng_length

strng_length std_logic_vector ( 3 downto 0 ) := ( others = > ' 0 ' )

Signal

toggle_channel

toggle_channel std_logic := ' 1 '

Signal

toggle_cnt

toggle_cnt std_logic_vector ( 1 downto 0 ) := ( others = > ' 0 ' )

Signal

ttc_str

ttc_str std_logic := ' 0 '

Signal

ttcclk

ttcclk std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• common/TTC_FMC/hdl/decoder_release_1.1/cdr2a_b_clk.vhd