clock_align_logic Entity Reference

Inheritance diagram for clock_align_logic:

Entities
rtl	architecture

Libraries
IEEE

Use Clauses
STD_LOGIC_1164
numeric_std

Ports
data_clk	in STD_LOGIC
ttc_clk	in std_logic
sel_phase	in std_logic
count_change	out std_logic

Member Data Documentation

count_change

count_change out std_logic

Port

data_clk

data_clk in STD_LOGIC

Port

IEEE

IEEE

Library

numeric_std

numeric_std

Package

sel_phase

sel_phase in std_logic

Port

STD_LOGIC_1164

STD_LOGIC_1164

Package

ttc_clk

ttc_clk in std_logic

Port

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The documentation for this class was generated from the following file:

• FTM/DSS/hdl/clock_align_logic.vhd