rtl Architecture Reference

Processes
clock2signal	( ttc_clk , ttc_toggle )
sync_pos	( data_clk , ttc_toggle , sreg )
sync_neg	( data_clk , ttc_toggle , sreg )
synch	( data_clk , sync_frame_in , sreg )
count_cycles	( data_clk , sync_pulse , count )
compare_cycles	( data_clk , count , prev_count )
start_up	( ttc_clk , running )

Constants
WAKEUP	integer := 6

Signals
sync_frame_in	std_logic := ' 0 '
sreg	std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )
sync_pulse	std_logic := ' 0 '
count	natural range 0 to 15 := 0
prev_count	natural range 0 to 15 := 0
this_count	natural range 0 to 15 := 0
running	std_logic_vector ( WAKEUP downto 0 ) := ( others = > ' 0 ' )
count_change_i	std_logic := ' 0 '
ttc_toggle	std_logic := ' 0 '
clock_pos	std_logic := ' 0 '
clock_neg	std_logic := ' 0 '

Member Function Documentation

clock2signal()

clock2signal (   ttc_clk ,   ttc_toggle   )

Process

compare_cycles()

compare_cycles (   data_clk ,   count ,   prev_count   )

Process

count_cycles()

count_cycles (   data_clk ,   sync_pulse ,   count   )

Process

start_up()

start_up (   ttc_clk ,   running   )

Process

sync_neg()

sync_neg (   data_clk ,   ttc_toggle ,   sreg   )

Process

sync_pos()

sync_pos (   data_clk ,   ttc_toggle ,   sreg   )

Process

synch()

synch (   data_clk ,   sync_frame_in ,   sreg   )

Process

Member Data Documentation

clock_neg

clock_neg std_logic := ' 0 '

Signal

clock_pos

clock_pos std_logic := ' 0 '

Signal

count

count natural range 0 to 15 := 0

Signal

count_change_i

count_change_i std_logic := ' 0 '

Signal

prev_count

prev_count natural range 0 to 15 := 0

Signal

running

running std_logic_vector ( WAKEUP downto 0 ) := ( others = > ' 0 ' )

Signal

sreg

sreg std_logic_vector ( 2 downto 0 ) := ( others = > ' 0 ' )

Signal

sync_frame_in

sync_frame_in std_logic := ' 0 '

Signal

sync_pulse

sync_pulse std_logic := ' 0 '

Signal

this_count

this_count natural range 0 to 15 := 0

Signal

ttc_toggle

ttc_toggle std_logic := ' 0 '

Signal

WAKEUP

WAKEUP integer := 6

Constant

---

The documentation for this class was generated from the following file:

• FTM/DSS/hdl/clock_align_logic.vhd