clock_sim Entity Reference

Inheritance diagram for clock_sim:

Entities
behavioural	architecture

Libraries
ieee

Use Clauses
std_logic_1164
numeric_std

Ports
clko125	out std_logic
clko25	out std_logic
clko40	out std_logic
clko62_5	out std_logic
nuke	in std_logic
soft_rst	in std_logic
rsto	out std_logic
rsto_ctrl	out std_logic

Member Data Documentation

clko125

clko125 out std_logic

Port

clko25

clko25 out std_logic

Port

clko40

clko40 out std_logic

Port

clko62_5

clko62_5 out std_logic

Port

ieee

ieee

Library

nuke

nuke in std_logic

Port

numeric_std

numeric_std

Package

rsto

rsto out std_logic

Port

rsto_ctrl

rsto_ctrl out std_logic

Port

soft_rst

soft_rst in std_logic

Port

std_logic_1164

std_logic_1164

Package

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/sim_hdl/clock_sim.vhd