behavioural Architecture Reference

Processes
PROCESS_367	( clk25 )
PROCESS_929	( clk25 )

Signals
clk125	std_logic := ' 0 '
clk25	std_logic := ' 0 '
clk40	std_logic := ' 0 '
clk62_5	std_logic := ' 0 '
nuke_del	std_logic := ' 0 '
srst	std_logic := ' 0 '
reset_vec	std_logic_vector ( 3 downto 0 ) := X " f "
rctr	unsigned ( 3 downto 0 ) := " 0000 "

Member Function Documentation

PROCESS_367()

PROCESS_367 (   clk25   )

Process

PROCESS_929()

PROCESS_929 (   clk25   )

Process

Member Data Documentation

clk125

clk125 std_logic := ' 0 '

Signal

clk25

clk25 std_logic := ' 0 '

Signal

clk40

clk40 std_logic := ' 0 '

Signal

clk62_5

clk62_5 std_logic := ' 0 '

Signal

nuke_del

nuke_del std_logic := ' 0 '

Signal

rctr

rctr unsigned ( 3 downto 0 ) := " 0000 "

Signal

reset_vec

reset_vec std_logic_vector ( 3 downto 0 ) := X " f "

Signal

srst

srst std_logic := ' 0 '

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/sim_hdl/clock_sim.vhd