testbench Architecture Reference

Processes
WaveGen_Proc	( )

Constants
clock_period	time := 3 . 6 ns
ttc_period	time := 25 . 0 ns

Signals
data_clk	STD_LOGIC := ' 0 '
ttc_clk	std_logic := ' 0 '
sel_phase	STD_LOGIC := ' 0 '
count_change	std_logic

Instantiations
dut	clock_align_logic <Entity clock_align_logic>

Member Function Documentation

WaveGen_Proc()

WaveGen_Proc

(

)

Member Data Documentation

clock_period

clock_period time := 3 . 6 ns

Constant

count_change

count_change std_logic

Signal

data_clk

data_clk STD_LOGIC := ' 0 '

Signal

dut

dut clock_align_logic

Instantiation

sel_phase

sel_phase STD_LOGIC := ' 0 '

Signal

ttc_clk

ttc_clk std_logic := ' 0 '

Signal

ttc_period

ttc_period time := 25 . 0 ns

Constant

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The documentation for this class was generated from the following file:

• testbench/clock_sync_logic_tb.vhd