clocks_7s_serdes Entity Reference

Inheritance diagram for clocks_7s_serdes:

Collaboration diagram for clocks_7s_serdes:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
VComponents

Ports
clki_fr	in std_logic
clki_125	in std_logic
clko_ipb	out std_logic
clko_p40	out std_logic
clko_200	out std_logic
eth_locked	in std_logic
locked	out std_logic
nuke	in std_logic
soft_rst	in std_logic
rsto_125	out std_logic
rsto_ipb	out std_logic
rsto_eth	out std_logic
rsto_ipb_ctrl	out std_logic
rsto_fr	out std_logic
onehz	out std_logic

Member Data Documentation

clki_125

clki_125 in std_logic

Port

clki_fr

clki_fr in std_logic

Port

clko_200

clko_200 out std_logic

Port

clko_ipb

clko_ipb out std_logic

Port

clko_p40

clko_p40 out std_logic

Port

eth_locked

eth_locked in std_logic

Port

ieee

ieee

Library

locked

locked out std_logic

Port

nuke

nuke in std_logic

Port

numeric_std

numeric_std

Package

onehz

onehz out std_logic

Port

rsto_125

rsto_125 out std_logic

Port

rsto_eth

rsto_eth out std_logic

Port

rsto_fr

rsto_fr out std_logic

Port

rsto_ipb

rsto_ipb out std_logic

Port

rsto_ipb_ctrl

rsto_ipb_ctrl out std_logic

Port

soft_rst

soft_rst in std_logic

Port

std_logic_1164

std_logic_1164

Package

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/clocks_7s_serdes.vhd