rtl Architecture Reference

Processes
PROCESS_317	( sysclk )
PROCESS_318	( clk_ipb_b )
PROCESS_319	( clk_ipb_b )
PROCESS_320	( clki_125 )
PROCESS_541	( sysclk )
PROCESS_542	( clk_ipb_b )
PROCESS_543	( clki_125 )
PROCESS_544	( sysclk )
PROCESS_878	( sysclk )
PROCESS_879	( clk_ipb_b )
PROCESS_880	( clk_ipb_b )
PROCESS_881	( clki_125 )

Signals
dcm_locked	std_logic
sysclk	std_logic
sysclk_ub	std_logic
clk_ipb_i	std_logic
clk_ipb_b	std_logic
clkfb	std_logic
clk_p40_i	std_logic
clk_p40_b	std_logic
d17	std_logic
d17_d	std_logic
nuke_i	std_logic := ' 0 '
nuke_d	std_logic := ' 0 '
nuke_d2	std_logic := ' 0 '
eth_done	std_logic := ' 0 '
rst	std_logic := ' 1 '
srst	std_logic := ' 1 '
rst_ipb	std_logic := ' 1 '
rst_125	std_logic := ' 1 '
rst_ipb_ctrl	std_logic := ' 1 '
rctr	unsigned ( 3 downto 0 ) := " 0000 "
rst_eth	std_logic := ' 1 '

Instantiations
bufgipb	bufg
bufgp40	bufg
mmcm	mmcme2_base
clkdiv	ipbus_clock_div <Entity ipbus_clock_div>
bufgipb	bufg
bufgp40	bufg
mmcm	mmcme2_base
clkdiv	clock_div <Entity clock_div>
bufgipb	bufg
bufgp40	bufg
mmcm	mmcme2_base
clkdiv	ipbus_clock_div <Entity ipbus_clock_div>

Member Function Documentation

PROCESS_317()

PROCESS_317

(

sysclk

)

PROCESS_318()

PROCESS_318 (   clk_ipb_b   )

Process

PROCESS_319()

PROCESS_319 (   clk_ipb_b   )

Process

PROCESS_320()

PROCESS_320 (   clki_125   )

Process

PROCESS_541()

PROCESS_541

(

sysclk

)

PROCESS_542()

PROCESS_542 (   clk_ipb_b   )

Process

PROCESS_543()

PROCESS_543 (   clki_125   )

Process

PROCESS_544()

PROCESS_544 (   sysclk   )

Process

PROCESS_878()

PROCESS_878

(

sysclk

)

PROCESS_879()

PROCESS_879 (   clk_ipb_b   )

Process

PROCESS_880()

PROCESS_880 (   clk_ipb_b   )

Process

PROCESS_881()

PROCESS_881 (   clki_125   )

Process

Member Data Documentation

bufgipb [1/3]

bufgipb bufg

Instantiation

bufgipb [2/3]

bufgipb bufg

Instantiation

bufgipb [3/3]

bufgipb bufg

Instantiation

bufgp40 [1/3]

bufgp40 bufg

Instantiation

bufgp40 [2/3]

bufgp40 bufg

Instantiation

bufgp40 [3/3]

bufgp40 bufg

Instantiation

clk_ipb_b

clk_ipb_b std_logic

Signal

clk_ipb_i

clk_ipb_i std_logic

Signal

clk_p40_b

clk_p40_b std_logic

Signal

clk_p40_i

clk_p40_i std_logic

Signal

clkdiv [1/3]

clkdiv clock_div

Instantiation

clkdiv [2/3]

clkdiv ipbus_clock_div

Instantiation

clkdiv [3/3]

clkdiv ipbus_clock_div

Instantiation

clkfb

clkfb std_logic

Signal

d17

d17 std_logic

Signal

d17_d

d17_d std_logic

Signal

dcm_locked

dcm_locked std_logic

Signal

eth_done

eth_done std_logic := ' 0 '

Signal

mmcm [1/3]

mmcm mmcme2_base

Instantiation

mmcm [2/3]

mmcm mmcme2_base

Instantiation

mmcm [3/3]

mmcm mmcme2_base

Instantiation

nuke_d

nuke_d std_logic := ' 0 '

Signal

nuke_d2

nuke_d2 std_logic := ' 0 '

Signal

nuke_i

nuke_i std_logic := ' 0 '

Signal

rctr

rctr unsigned ( 3 downto 0 ) := " 0000 "

Signal

rst

rst std_logic := ' 1 '

Signal

rst_125

rst_125 std_logic := ' 1 '

Signal

rst_eth

rst_eth std_logic := ' 1 '

Signal

rst_ipb

rst_ipb std_logic := ' 1 '

Signal

rst_ipb_ctrl

rst_ipb_ctrl std_logic := ' 1 '

Signal

srst

srst std_logic := ' 1 '

Signal

sysclk

sysclk std_logic

Signal

sysclk_ub

sysclk_ub std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/clocks_7s_serdes.vhd