My Project  v0.0.16
Ports | Libraries | Use Clauses
clocks_dss_algo Entity Reference
Inheritance diagram for clocks_dss_algo:
Inheritance graph
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Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
VComponents 

Ports

ttc_clock   in std_logic
clko_40   out std_logic
clko_200   out std_logic
load_algo   out std_logic
locked   out std_logic

Member Data Documentation

◆ clko_200

clko_200 out std_logic
Port

◆ clko_40

clko_40 out std_logic
Port

◆ ieee

ieee
Library

◆ load_algo

load_algo out std_logic
Port

◆ locked

locked out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ ttc_clock

ttc_clock in std_logic
Port

◆ unisim

unisim
Library

◆ VComponents

VComponents
Package

The documentation for this class was generated from the following file: