rtl Architecture Reference

Signals
dcm_locked	std_logic
sysclk	std_logic
clk_40_i	std_logic
clk_200_i	std_logic
load_40_i	std_logic
clkfb	std_logic
rst	std_logic := ' 1 '
clkfbout	std_logic

Instantiations
bufg200	bufg
bufg40	bufg
bufgload	bufg
bufgfb	bufg
mmcm	mmcme2_base

Member Data Documentation

bufg200

bufg200 bufg

Instantiation

bufg40

bufg40 bufg

Instantiation

bufgfb

bufgfb bufg

Instantiation

bufgload

bufgload bufg

Instantiation

clk_200_i

clk_200_i std_logic

Signal

clk_40_i

clk_40_i std_logic

Signal

clkfb

clkfb std_logic

Signal

clkfbout

clkfbout std_logic

Signal

dcm_locked

dcm_locked std_logic

Signal

load_40_i

load_40_i std_logic

Signal

mmcm

mmcm mmcme2_base

Instantiation

rst

rst std_logic := ' 1 '

Signal

sysclk

sysclk std_logic

Signal

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The documentation for this class was generated from the following file:

• FTM/DSS_Algo/hdl/clocks_dss_algo.vhd