rtl Architecture Reference

Processes
PROCESS_344	( sysclk )
PROCESS_345	( clk_ipb_b )
PROCESS_346	( clki_125 )
PROCESS_347	( sysclk )
PROCESS_568	( sysclk )
PROCESS_569	( clk_ipb_b )
PROCESS_570	( clki_125 )
PROCESS_571	( sysclk )
PROCESS_906	( sysclk )
PROCESS_907	( clk_ipb_b )
PROCESS_908	( clki_125 )
PROCESS_909	( sysclk )

Signals
dcm_locked	std_logic
sysclk	std_logic
sysclk_ub	std_logic
clk_ipb_i	std_logic
clk_ipb_b	std_logic
clkfb	std_logic
d17	std_logic
d17_d	std_logic
nuke_i	std_logic := ' 0 '
nuke_d	std_logic := ' 0 '
nuke_d2	std_logic := ' 0 '
rst	std_logic := ' 1 '
rst_ipb	std_logic := ' 1 '
rst_125	std_logic := ' 1 '
rst_eth	std_logic := ' 1 '

Instantiations
ibufgds0	ibufgds
bufg_sys	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_div <Entity clock_div>
ibufgds0	ibufgds
bufg_sys	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_div <Entity clock_div>
ibufgds0	ibufgds
bufg_sys	bufg
bufgipb	bufg
mmcm	mmcm_base
clkdiv	clock_div <Entity clock_div>

Member Function Documentation

PROCESS_344()

PROCESS_344

(

sysclk

)

PROCESS_345()

PROCESS_345 (   clk_ipb_b   )

Process

PROCESS_346()

PROCESS_346 (   clki_125   )

Process

PROCESS_347()

PROCESS_347 (   sysclk   )

Process

PROCESS_568()

PROCESS_568

(

sysclk

)

PROCESS_569()

PROCESS_569 (   clk_ipb_b   )

Process

PROCESS_570()

PROCESS_570 (   clki_125   )

Process

PROCESS_571()

PROCESS_571 (   sysclk   )

Process

PROCESS_906()

PROCESS_906

(

sysclk

)

PROCESS_907()

PROCESS_907 (   clk_ipb_b   )

Process

PROCESS_908()

PROCESS_908 (   clki_125   )

Process

PROCESS_909()

PROCESS_909 (   sysclk   )

Process

Member Data Documentation

bufg_sys [1/3]

bufg_sys bufg

Instantiation

bufg_sys [2/3]

bufg_sys bufg

Instantiation

bufg_sys [3/3]

bufg_sys bufg

Instantiation

bufgipb [1/3]

bufgipb bufg

Instantiation

bufgipb [2/3]

bufgipb bufg

Instantiation

bufgipb [3/3]

bufgipb bufg

Instantiation

clk_ipb_b

clk_ipb_b std_logic

Signal

clk_ipb_i

clk_ipb_i std_logic

Signal

clkdiv [1/3]

clkdiv clock_div

Instantiation

clkdiv [2/3]

clkdiv clock_div

Instantiation

clkdiv [3/3]

clkdiv clock_div

Instantiation

clkfb

clkfb std_logic

Signal

d17

d17 std_logic

Signal

d17_d

d17_d std_logic

Signal

dcm_locked

dcm_locked std_logic

Signal

ibufgds0 [1/3]

ibufgds0 ibufgds

Instantiation

ibufgds0 [2/3]

ibufgds0 ibufgds

Instantiation

ibufgds0 [3/3]

ibufgds0 ibufgds

Instantiation

mmcm [1/3]

mmcm mmcm_base

Instantiation

mmcm [2/3]

mmcm mmcm_base

Instantiation

mmcm [3/3]

mmcm mmcm_base

Instantiation

nuke_d

nuke_d std_logic := ' 0 '

Signal

nuke_d2

nuke_d2 std_logic := ' 0 '

Signal

nuke_i

nuke_i std_logic := ' 0 '

Signal

rst

rst std_logic := ' 1 '

Signal

rst_125

rst_125 std_logic := ' 1 '

Signal

rst_eth

rst_eth std_logic := ' 1 '

Signal

rst_ipb

rst_ipb std_logic := ' 1 '

Signal

sysclk

sysclk std_logic

Signal

sysclk_ub

sysclk_ub std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_util/firmware/hdl/clocks_v6_serdes_125MHz.vhd