My Project
v0.0.16
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Entities | |
rtl | architecture |
Libraries | |
IEEE | |
unisim |
Use Clauses | |
STD_LOGIC_1164 | |
VComponents | |
ftm | Package <ftm> |
Ports | |
mgtdata | in mgt_data |
clock | in std_logic |
monitor | out std_logic |
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Port |
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Package |
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Library |
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Port |
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Package |
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Library |
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