rtl Architecture Reference

Processes
stretch	( clock , marker , pulse )

Constants
WIDTH	positive := 4

Signals
marker	std_logic := ' 0 '
pulse	std_logic_vector ( WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Member Function Documentation

stretch()

stretch (   clock ,   marker ,   pulse   )

Process

Member Data Documentation

marker

marker std_logic := ' 0 '

Signal

pulse

pulse std_logic_vector ( WIDTH - 1 downto 0 ) := ( others = > ' 0 ' )

Signal

WIDTH

WIDTH positive := 4

Constant

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The documentation for this class was generated from the following file:

• FTM/DSS/hdl/comma_monitor.vhd