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My Project
v0.0.16
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Processes | |
| PROCESS_14 | ( clock , data_in ) |
| PROCESS_948 | ( clock , data_in ) |
Constants | |
| DELAY | time := 2 ns |
Signals | |
| retimed_data | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| data_int | std_logic_vector ( 31 downto 0 ) := ( others = > ' 0 ' ) |
| insert_crc | std_logic := ' 0 ' |
| crc_word_en | std_logic := ' 0 ' |
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Signal |
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Signal |
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Constant |
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Signal |
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Signal |
1.8.13