My Project
v0.0.16
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Processes | |
PROCESS_361 | ( clk_f ) |
PROCESS_362 | ( clk_s ) |
PROCESS_923 | ( clk_f ) |
PROCESS_924 | ( clk_s ) |
Signals | |
ctr | integer range RATIO - 1 downto 0 := 0 |
d | std_logic_vector ( DWIDTH * RATIO - 1 downto 0 ) |
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Process |
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Process |
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Process |
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Process |