Behavioral Architecture Reference

Processes
reader	( CLK )

Constants
clk_half_one	unsigned ( 7 downto 0 ) := x " 3F "
clk_full_one	unsigned ( 7 downto 0 ) := x " 7F "
clk_half_zero	unsigned ( 7 downto 0 ) := x " BF "
clk_full	unsigned ( 7 downto 0 ) := x " FF "
control_r	std_logic_vector ( 7 downto 0 ) := x " A1 "
control_w	std_logic_vector ( 7 downto 0 ) := x " A0 "

Types
StateType	( start , controlW , wait_ack , address , wait_ack2 , start2 , controlR , wait_ack3 , data , issue_ack , issue_no_ack , stop , dead )

Signals
busy_int	std_logic
scl_int	std_logic
sda_o_int	std_logic
state	StateType
clk_counter	unsigned ( 7 downto 0 )
i	unsigned ( 7 downto 0 )
words	unsigned ( 7 downto 0 )
data_int	std_logic_vector ( 63 downto 0 )
rec_bit	std_logic
bit_rec	std_logic

Member Function Documentation

reader()

reader (   CLK   )

Process

Member Data Documentation

bit_rec

bit_rec std_logic

Signal

busy_int

busy_int std_logic

Signal

clk_counter

clk_counter unsigned ( 7 downto 0 )

Signal

clk_full

clk_full unsigned ( 7 downto 0 ) := x " FF "

Constant

clk_full_one

clk_full_one unsigned ( 7 downto 0 ) := x " 7F "

Constant

clk_half_one

clk_half_one unsigned ( 7 downto 0 ) := x " 3F "

Constant

clk_half_zero

clk_half_zero unsigned ( 7 downto 0 ) := x " BF "

Constant

control_r

control_r std_logic_vector ( 7 downto 0 ) := x " A1 "

Constant

control_w

control_w std_logic_vector ( 7 downto 0 ) := x " A0 "

Constant

data_int

data_int std_logic_vector ( 63 downto 0 )

Signal

i

i unsigned ( 7 downto 0 )

Signal

rec_bit

rec_bit std_logic

Signal

scl_int

scl_int std_logic

Signal

sda_o_int

sda_o_int std_logic

Signal

state

state StateType

Signal

StateType

StateType ( start , controlW , wait_ack , address , wait_ack2 , start2 , controlR , wait_ack3 , data , issue_ack , issue_no_ack , stop , dead )

Type

words

words unsigned ( 7 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• FTM/Control/hdl/eeprom_addr_reader.vhd