eth_7s_1000basex Entity Reference

Inheritance diagram for eth_7s_1000basex:

Collaboration diagram for eth_7s_1000basex:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
VComponents
emac_hostbus_decl	Package <emac_hostbus_decl>

Ports
gt_clkp	in std_logic
gt_clkn	in std_logic
gt_txp	out std_logic
gt_txn	out std_logic
gt_rxp	in std_logic
gt_rxn	in std_logic
clk125_out	out std_logic
clk125_fr	out std_logic
rsti	in std_logic
locked	out std_logic
tx_data	in std_logic_vector ( 7 downto 0 )
tx_valid	in std_logic
tx_last	in std_logic
tx_error	in std_logic
tx_ready	out std_logic
rx_data	out std_logic_vector ( 7 downto 0 )
rx_valid	out std_logic
rx_last	out std_logic
rx_error	out std_logic
hostbus_in	in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )
hostbus_out	out emac_hostbus_out
refclk_out	out std_logic
sig_detn	in std_logic := ' 1 '

Member Data Documentation

clk125_fr

clk125_fr out std_logic

Port

clk125_out

clk125_out out std_logic

Port

emac_hostbus_decl

emac_hostbus_decl

Package

gt_clkn

gt_clkn in std_logic

Port

gt_clkp

gt_clkp in std_logic

Port

gt_rxn

gt_rxn in std_logic

Port

gt_rxp

gt_rxp in std_logic

Port

gt_txn

gt_txn out std_logic

Port

gt_txp

gt_txp out std_logic

Port

hostbus_in

hostbus_in in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )

Port

hostbus_out

hostbus_out out emac_hostbus_out

Port

ieee

ieee

Library

locked

locked out std_logic

Port

refclk_out

refclk_out out std_logic

Port

rsti

rsti in std_logic

Port

rx_data

rx_data out std_logic_vector ( 7 downto 0 )

Port

rx_error

rx_error out std_logic

Port

rx_last

rx_last out std_logic

Port

rx_valid

rx_valid out std_logic

Port

sig_detn

sig_detn in std_logic := ' 1 '

Port

std_logic_1164

std_logic_1164

Package

tx_data

tx_data in std_logic_vector ( 7 downto 0 )

Port

tx_error

tx_error in std_logic

Port

tx_last

tx_last in std_logic

Port

tx_ready

tx_ready out std_logic

Port

tx_valid

tx_valid in std_logic

Port

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following files:

• components/ipbus_eth/firmware/hdl/eth_7s_1000basex.vhd
• components/ipbus_eth/firmware/hdl/eth_7s_1000basex_gth.vhd
• components/ipbus_eth/firmware/hdl/eth_7s_1000basex_gth_viv.vhd
• components/ipbus_eth/firmware/hdl/eth_7s_1000basex_new.vhd