My Project  v0.0.16
Components | Signals | Processes | Instantiations
rtl Architecture Reference

Processes

PROCESS_257  ( clk_fr )
PROCESS_258  ( clk_fr )
PROCESS_259  ( clk_fr )
PROCESS_260  ( clk_fr )
PROCESS_261  ( clk_fr )
PROCESS_262  ( clk_fr )
PROCESS_585  ( clk_fr )
PROCESS_818  ( clk_fr )
PROCESS_819  ( clk_fr )

Components

tri_mode_eth_mac_v5_5 
tri_mode_eth_mac_v8_3 
gig_ethernet_pcs_pma_0_block 
temac_gbe_v9_0 
gig_eth_pcs_pma_basex_v15_0  <Entity gig_eth_pcs_pma_basex_v15_0>

Signals

gmii_txd  std_logic_vector ( 7 downto 0 )
gmii_rxd  std_logic_vector ( 7 downto 0 )
gmii_tx_en  std_logic
gmii_tx_er  std_logic
gmii_rx_dv  std_logic
gmii_rx_er  std_logic
gmii_rx_clk  std_logic
clkin  std_logic
clk125  std_logic
txoutclk_ub  std_logic
txoutclk  std_logic
clk125_ub  std_logic
clk_fr  std_logic
clk62_5_ub  std_logic
clk62_5  std_logic
clkfb  std_logic
rstn  std_logic
phy_done  std_logic
mmcm_locked  std_logic
locked_int  std_logic
status  std_logic_vector ( 15 downto 0 )
decoupled_clk  std_logic := ' 0 '
decoupled_clk_src  std_logic := ' 0 '
sig_det  std_logic
mmcm_reset  std_logic
mmcm_reset_phy  std_logic

Instantiations

ibuf0  ibufds_gte2
bufg_fr  bufg
bufg_tx  bufh
mcmm  mmcme2_base
bufr_125  bufh
bufr_62_5  bufh
mac  tri_mode_eth_mac_v5_5
phy  gig_eth_pcs_pma_v11_5_block <Entity gig_eth_pcs_pma_v11_5_block>
ibuf0  ibufds_gte2
bufg_fr  bufg
bufh_tx  bufh
mmcm  mmcme2_base
bufr_125  bufh
bufr_62_5  bufh
mac  tri_mode_eth_mac_v5_5
buf_decoupled_clk  bufh
phy  gig_eth_pcs_pma_v11_5_block <Entity gig_eth_pcs_pma_v11_5_block>
ibuf0  ibufds_gte2
bufg_fr  bufg
bufh_tx  bufh
mmcm  mmcme2_base
bufr_125  bufh
bufr_62_5  bufh
mac  tri_mode_eth_mac_v8_3
phy  gig_ethernet_pcs_pma_0_block
ibuf0  ibufds_gte2
bufg_fr  bufg
bufg_tx  bufg
mcmm  mmcme2_base
bufg_125  bufg
bufg_62_5  bufg
mac  tri_mode_eth_mac_v5_5
phy  gig_eth_pcs_pma_v11_5_block <Entity gig_eth_pcs_pma_v11_5_block>
ibuf0  ibufds_gte2
bufg_fr  bufg
bufg_tx  bufg
mcmm  mmcme2_base
bufg_125  bufg
bufg_62_5  bufg
mac  tri_mode_eth_mac_v5_5
phy  gig_eth_pcs_pma_v11_4_block
ibuf0  ibufds_gte2
bufg_fr  bufg
bufh_tx  bufh
mmcm  mmcme2_base
bufr_125  bufh
bufr_62_5  bufh
mac  temac_gbe_v9_0
phy  gig_eth_pcs_pma_basex_v15_0 <Entity gig_eth_pcs_pma_basex_v15_0>

Member Function Documentation

◆ PROCESS_257()

PROCESS_257 (   clk_fr)

◆ PROCESS_258()

PROCESS_258 (   clk_fr)

◆ PROCESS_259()

PROCESS_259 (   clk_fr)

◆ PROCESS_260()

PROCESS_260 (   clk_fr)

◆ PROCESS_261()

PROCESS_261 (   clk_fr)

◆ PROCESS_262()

PROCESS_262 (   clk_fr)

◆ PROCESS_585()

PROCESS_585 (   clk_fr)

◆ PROCESS_818()

PROCESS_818 (   clk_fr)

◆ PROCESS_819()

PROCESS_819 (   clk_fr)

Member Data Documentation

◆ buf_decoupled_clk

buf_decoupled_clk bufh
Instantiation

◆ bufg_125 [1/2]

bufg_125 bufg
Instantiation

◆ bufg_125 [2/2]

bufg_125 bufg
Instantiation

◆ bufg_62_5 [1/2]

bufg_62_5 bufg
Instantiation

◆ bufg_62_5 [2/2]

bufg_62_5 bufg
Instantiation

◆ bufg_fr [1/6]

bufg_fr bufg
Instantiation

◆ bufg_fr [2/6]

bufg_fr bufg
Instantiation

◆ bufg_fr [3/6]

bufg_fr bufg
Instantiation

◆ bufg_fr [4/6]

bufg_fr bufg
Instantiation

◆ bufg_fr [5/6]

bufg_fr bufg
Instantiation

◆ bufg_fr [6/6]

bufg_fr bufg
Instantiation

◆ bufg_tx [1/3]

bufg_tx bufg
Instantiation

◆ bufg_tx [2/3]

bufg_tx bufh
Instantiation

◆ bufg_tx [3/3]

bufg_tx bufg
Instantiation

◆ bufh_tx [1/3]

bufh_tx bufh
Instantiation

◆ bufh_tx [2/3]

bufh_tx bufh
Instantiation

◆ bufh_tx [3/3]

bufh_tx bufh
Instantiation

◆ bufr_125 [1/4]

bufr_125 bufh
Instantiation

◆ bufr_125 [2/4]

bufr_125 bufh
Instantiation

◆ bufr_125 [3/4]

bufr_125 bufh
Instantiation

◆ bufr_125 [4/4]

bufr_125 bufh
Instantiation

◆ bufr_62_5 [1/4]

bufr_62_5 bufh
Instantiation

◆ bufr_62_5 [2/4]

bufr_62_5 bufh
Instantiation

◆ bufr_62_5 [3/4]

bufr_62_5 bufh
Instantiation

◆ bufr_62_5 [4/4]

bufr_62_5 bufh
Instantiation

◆ clk125

clk125 std_logic
Signal

◆ clk125_ub

clk125_ub std_logic
Signal

◆ clk62_5

clk62_5 std_logic
Signal

◆ clk62_5_ub

clk62_5_ub std_logic
Signal

◆ clk_fr

clk_fr std_logic
Signal

◆ clkfb

clkfb std_logic
Signal

◆ clkin

clkin std_logic
Signal

◆ decoupled_clk

decoupled_clk std_logic := ' 0 '
Signal

◆ decoupled_clk_src

decoupled_clk_src std_logic := ' 0 '
Signal

◆ gig_eth_pcs_pma_basex_v15_0

◆ gig_ethernet_pcs_pma_0_block

◆ gmii_rx_clk

gmii_rx_clk std_logic
Signal

◆ gmii_rx_dv

gmii_rx_dv std_logic
Signal

◆ gmii_rx_er

gmii_rx_er std_logic
Signal

◆ gmii_rxd

gmii_rxd std_logic_vector ( 7 downto 0 )
Signal

◆ gmii_tx_en

gmii_tx_en std_logic
Signal

◆ gmii_tx_er

gmii_tx_er std_logic
Signal

◆ gmii_txd

gmii_txd std_logic_vector ( 7 downto 0 )
Signal

◆ ibuf0 [1/6]

ibuf0 ibufds_gte2
Instantiation

◆ ibuf0 [2/6]

ibuf0 ibufds_gte2
Instantiation

◆ ibuf0 [3/6]

ibuf0 ibufds_gte2
Instantiation

◆ ibuf0 [4/6]

ibuf0 ibufds_gte2
Instantiation

◆ ibuf0 [5/6]

ibuf0 ibufds_gte2
Instantiation

◆ ibuf0 [6/6]

ibuf0 ibufds_gte2
Instantiation

◆ locked_int

locked_int std_logic
Signal

◆ mac [1/6]

mac tri_mode_eth_mac_v5_5
Instantiation

◆ mac [2/6]

mac tri_mode_eth_mac_v5_5
Instantiation

◆ mac [3/6]

mac tri_mode_eth_mac_v5_5
Instantiation

◆ mac [4/6]

mac tri_mode_eth_mac_v5_5
Instantiation

◆ mac [5/6]

mac tri_mode_eth_mac_v8_3
Instantiation

◆ mac [6/6]

mac temac_gbe_v9_0
Instantiation

◆ mcmm [1/3]

mcmm mmcme2_base
Instantiation

◆ mcmm [2/3]

mcmm mmcme2_base
Instantiation

◆ mcmm [3/3]

mcmm mmcme2_base
Instantiation

◆ mmcm [1/3]

mmcm mmcme2_base
Instantiation

◆ mmcm [2/3]

mmcm mmcme2_base
Instantiation

◆ mmcm [3/3]

mmcm mmcme2_base
Instantiation

◆ mmcm_locked

mmcm_locked std_logic
Signal

◆ mmcm_reset

mmcm_reset std_logic
Signal

◆ mmcm_reset_phy

mmcm_reset_phy std_logic
Signal

◆ phy [1/6]

phy gig_eth_pcs_pma_v11_4_block
Instantiation

◆ phy [2/6]

phy gig_eth_pcs_pma_v11_5_block
Instantiation

◆ phy [3/6]

phy gig_eth_pcs_pma_v11_5_block
Instantiation

◆ phy [4/6]

phy gig_eth_pcs_pma_v11_5_block
Instantiation

◆ phy [5/6]

phy gig_ethernet_pcs_pma_0_block
Instantiation

◆ phy [6/6]

phy gig_eth_pcs_pma_basex_v15_0
Instantiation

◆ phy_done

phy_done std_logic
Signal

◆ rstn

rstn std_logic
Signal

◆ sig_det

sig_det std_logic
Signal

◆ status

status std_logic_vector ( 15 downto 0 )
Signal

◆ temac_gbe_v9_0

temac_gbe_v9_0
Component

◆ tri_mode_eth_mac_v5_5

◆ tri_mode_eth_mac_v8_3

◆ txoutclk

txoutclk std_logic
Signal

◆ txoutclk_ub

txoutclk_ub std_logic
Signal

The documentation for this class was generated from the following files: