eth_v5_gmii Entity Reference

Inheritance diagram for eth_v5_gmii:

Collaboration diagram for eth_v5_gmii:

Entities
rtl	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
VComponents
emac_hostbus_decl	Package <emac_hostbus_decl>

Ports
clk125	in std_logic
clk200	in std_logic
rst	in std_logic
locked	in std_logic
gmii_tx_clk	out std_logic
gmii_txd	out std_logic_vector ( 7 downto 0 )
gmii_tx_en	out std_logic
gmii_tx_er	out std_logic
gmii_rx_clk	in std_logic
gmii_rxd	in std_logic_vector ( 7 downto 0 )
gmii_rx_dv	in std_logic
gmii_rx_er	in std_logic
tx_data	in std_logic_vector ( 7 downto 0 )
tx_valid	in std_logic
tx_last	in std_logic
tx_error	in std_logic
tx_ready	out std_logic
rx_data	out std_logic_vector ( 7 downto 0 )
rx_valid	out std_logic
rx_last	out std_logic
rx_error	out std_logic
hostbus_in	in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )
hostbus_out	out emac_hostbus_out

Member Data Documentation

clk125

clk125 in std_logic

Port

clk200

clk200 in std_logic

Port

emac_hostbus_decl

emac_hostbus_decl

Package

gmii_rx_clk

gmii_rx_clk in std_logic

Port

gmii_rx_dv

gmii_rx_dv in std_logic

Port

gmii_rx_er

gmii_rx_er in std_logic

Port

gmii_rxd

gmii_rxd in std_logic_vector ( 7 downto 0 )

Port

gmii_tx_clk

gmii_tx_clk out std_logic

Port

gmii_tx_en

gmii_tx_en out std_logic

Port

gmii_tx_er

gmii_tx_er out std_logic

Port

gmii_txd

gmii_txd out std_logic_vector ( 7 downto 0 )

Port

hostbus_in

hostbus_in in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )

Port

hostbus_out

hostbus_out out emac_hostbus_out

Port

ieee

ieee

Library

locked

locked in std_logic

Port

rst

rst in std_logic

Port

rx_data

rx_data out std_logic_vector ( 7 downto 0 )

Port

rx_error

rx_error out std_logic

Port

rx_last

rx_last out std_logic

Port

rx_valid

rx_valid out std_logic

Port

std_logic_1164

std_logic_1164

Package

tx_data

tx_data in std_logic_vector ( 7 downto 0 )

Port

tx_error

tx_error in std_logic

Port

tx_last

tx_last in std_logic

Port

tx_ready

tx_ready out std_logic

Port

tx_valid

tx_valid in std_logic

Port

unisim

unisim

Library

VComponents

VComponents

Package

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_v5_gmii.vhd