My Project
v0.0.16
|
Entities | |
rtl | architecture |
Libraries | |
ieee | |
unisim |
Use Clauses | |
std_logic_1164 | |
VComponents | |
emac_hostbus_decl | Package <emac_hostbus_decl> |
Ports | |
sgmii_clkp | in std_logic |
sgmii_clkn | in std_logic |
sgmii_txp | out std_logic |
sgmii_txn | out std_logic |
sgmii_rxp | in std_logic |
sgmii_rxn | in std_logic |
sync_acq | out std_logic |
clk125_o | out std_logic |
clk125_fr | out std_logic |
rst | in std_logic |
locked | out std_logic |
tx_data | in std_logic_vector ( 7 downto 0 ) |
tx_valid | in std_logic |
tx_last | in std_logic |
tx_error | in std_logic |
tx_ready | out std_logic |
rx_data | out std_logic_vector ( 7 downto 0 ) |
rx_valid | out std_logic |
rx_last | out std_logic |
rx_error | out std_logic |
hostbus_in | in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' ) |
hostbus_out | out emac_hostbus_out |
|
Port |
|
Port |
|
Package |
|
Port |
|
Port |
|
Library |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Package |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Port |
|
Library |
|
Package |