My Project  v0.0.16
Ports | Libraries | Use Clauses
eth_v6_sgmii Entity Reference
Inheritance diagram for eth_v6_sgmii:
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Collaboration diagram for eth_v6_sgmii:
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Entities

rtl  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
VComponents 
emac_hostbus_decl  Package <emac_hostbus_decl>

Ports

sgmii_clkp   in std_logic
sgmii_clkn   in std_logic
sgmii_txp   out std_logic
sgmii_txn   out std_logic
sgmii_rxp   in std_logic
sgmii_rxn   in std_logic
sync_acq   out std_logic
clk125_o   out std_logic
clk125_fr   out std_logic
rst   in std_logic
locked   out std_logic
tx_data   in std_logic_vector ( 7 downto 0 )
tx_valid   in std_logic
tx_last   in std_logic
tx_error   in std_logic
tx_ready   out std_logic
rx_data   out std_logic_vector ( 7 downto 0 )
rx_valid   out std_logic
rx_last   out std_logic
rx_error   out std_logic
hostbus_in   in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )
hostbus_out   out emac_hostbus_out

Member Data Documentation

◆ clk125_fr

clk125_fr out std_logic
Port

◆ clk125_o

clk125_o out std_logic
Port

◆ emac_hostbus_decl

◆ hostbus_in

hostbus_in in emac_hostbus_in := ( ' 0 ' , " 00 " , " 0000000000 " , X " 00000000 " , ' 0 ' , ' 0 ' , ' 0 ' )
Port

◆ hostbus_out

◆ ieee

ieee
Library

◆ locked

locked out std_logic
Port

◆ rst

rst in std_logic
Port

◆ rx_data

rx_data out std_logic_vector ( 7 downto 0 )
Port

◆ rx_error

rx_error out std_logic
Port

◆ rx_last

rx_last out std_logic
Port

◆ rx_valid

rx_valid out std_logic
Port

◆ sgmii_clkn

sgmii_clkn in std_logic
Port

◆ sgmii_clkp

sgmii_clkp in std_logic
Port

◆ sgmii_rxn

sgmii_rxn in std_logic
Port

◆ sgmii_rxp

sgmii_rxp in std_logic
Port

◆ sgmii_txn

sgmii_txn out std_logic
Port

◆ sgmii_txp

sgmii_txp out std_logic
Port

◆ std_logic_1164

std_logic_1164
Package

◆ sync_acq

sync_acq out std_logic
Port

◆ tx_data

tx_data in std_logic_vector ( 7 downto 0 )
Port

◆ tx_error

tx_error in std_logic
Port

◆ tx_last

tx_last in std_logic
Port

◆ tx_ready

tx_ready out std_logic
Port

◆ tx_valid

tx_valid in std_logic
Port

◆ unisim

unisim
Library

◆ VComponents

VComponents
Package

The documentation for this class was generated from the following file: