rtl Architecture Reference

Signals
clkin	std_logic
clk125	std_logic
clk125_out	std_logic
clkp	std_logic
clkn	std_logic
rstn	std_logic
resetdone	std_logic
syncacqstatus	std_logic

Instantiations
clkbuf	ibufds_gtxe1
bufg_d	bufg
bufg0	bufg
sgmii	v6_emac_v2_3_sgmii_block <Entity v6_emac_v2_3_sgmii_block>
clkbuf	ibufds_gtxe1
bufg_d	bufg
bufg0	bufg
sgmii	v6_emac_v2_3_sgmii_block <Entity v6_emac_v2_3_sgmii_block>

Member Data Documentation

bufg0 [1/2]

bufg0 bufg

Instantiation

bufg0 [2/2]

bufg0 bufg

Instantiation

bufg_d [1/2]

bufg_d bufg

Instantiation

bufg_d [2/2]

bufg_d bufg

Instantiation

clk125

clk125 std_logic

Signal

clk125_out

clk125_out std_logic

Signal

clkbuf [1/2]

clkbuf ibufds_gtxe1

Instantiation

clkbuf [2/2]

clkbuf ibufds_gtxe1

Instantiation

clkin

clkin std_logic

Signal

clkn

clkn std_logic

Signal

clkp

clkp std_logic

Signal

resetdone

resetdone std_logic

Signal

rstn

rstn std_logic

Signal

sgmii [1/2]

sgmii v6_emac_v2_3_sgmii_block

Instantiation

sgmii [2/2]

sgmii v6_emac_v2_3_sgmii_block

Instantiation

syncacqstatus

syncacqstatus std_logic

Signal

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The documentation for this class was generated from the following file:

• components/ipbus_eth/firmware/hdl/eth_v6_sgmii.vhd