ext_align_gth_32b_10g_spartan Entity Reference

Inheritance diagram for ext_align_gth_32b_10g_spartan:

Collaboration diagram for ext_align_gth_32b_10g_spartan:

Entities
behave	architecture

Libraries
ieee
unisim

Use Clauses
std_logic_1164
numeric_std
vcomponents
package_links
package_types
package_utilities

Generics
SIM_GTRESET_SPEEDUP	string := " TRUE "
SIMULATION	integer := 0
LOCAL_LHC_CLK_MULTIPLE	integer := 4
LOCAL_LHC_BUNCH_COUNT	integer
X_LOC	integer
Y_LOC	integer

Ports
ttc_clk_in	in std_logic
ttc_rst_in	in std_logic
refclk_in	in std_logic
drpclk_in	in std_logic
sysclk_in	in std_logic
common_drp_address_in	in std_logic_vector ( 7 downto 0 )
common_drp_data_in	in std_logic_vector ( 15 downto 0 )
common_drp_data_out	out std_logic_vector ( 15 downto 0 )
common_drp_enable_in	in std_logic
common_drp_ready_out	out std_logic
common_drp_write_in	in std_logic
rxn_in	in std_logic_vector ( 3 downto 0 )
rxp_in	in std_logic_vector ( 3 downto 0 )
txn_out	out std_logic_vector ( 3 downto 0 )
txp_out	out std_logic_vector ( 3 downto 0 )
chan_drp_address_in	in type_drp_addr_array ( 3 downto 0 )
chan_drp_data_in	in type_drp_data_array ( 3 downto 0 )
chan_drp_data_out	out type_drp_data_array ( 3 downto 0 )
chan_drp_enable_in	in std_logic_vector ( 3 downto 0 )
chan_drp_ready_out	out std_logic_vector ( 3 downto 0 )
chan_drp_write_in	in std_logic_vector ( 3 downto 0 )
txdata_in	in type_32b_data_array ( 3 downto 0 )
txdatavalid_in	in std_logic_vector ( 3 downto 0 )
rxdata_out	out type_32b_data_array ( 3 downto 0 )
rxdatavalid_out	out std_logic_vector ( 3 downto 0 )
buf_master_in	in std_logic_vector ( 3 downto 0 )
buf_rst_in	in std_logic
buf_ptr_inc_in	in std_logic_vector ( 3 downto 0 )
buf_ptr_dec_in	in std_logic_vector ( 3 downto 0 )
align_marker_out	out std_logic_vector ( 3 downto 0 )
chan_ro_regs_out	out type_chan_ro_reg_array ( 3 downto 0 )
chan_rw_regs_in	in type_chan_rw_reg_array ( 3 downto 0 )
common_ro_regs_out	out type_common_ro_reg
common_rw_regs_in	in type_common_rw_reg
qplllock	out std_logic
txclk_mon	out std_logic
rxclk_mon	out std_logic_vector ( 3 downto 0 )

Member Data Documentation

align_marker_out

align_marker_out out std_logic_vector ( 3 downto 0 )

Port

buf_master_in

buf_master_in in std_logic_vector ( 3 downto 0 )

Port

buf_ptr_dec_in

buf_ptr_dec_in in std_logic_vector ( 3 downto 0 )

Port

buf_ptr_inc_in

buf_ptr_inc_in in std_logic_vector ( 3 downto 0 )

Port

buf_rst_in

buf_rst_in in std_logic

Port

chan_drp_address_in

chan_drp_address_in in type_drp_addr_array ( 3 downto 0 )

Port

chan_drp_data_in

chan_drp_data_in in type_drp_data_array ( 3 downto 0 )

Port

chan_drp_data_out

chan_drp_data_out out type_drp_data_array ( 3 downto 0 )

Port

chan_drp_enable_in

chan_drp_enable_in in std_logic_vector ( 3 downto 0 )

Port

chan_drp_ready_out

chan_drp_ready_out out std_logic_vector ( 3 downto 0 )

Port

chan_drp_write_in

chan_drp_write_in in std_logic_vector ( 3 downto 0 )

Port

chan_ro_regs_out

chan_ro_regs_out out type_chan_ro_reg_array ( 3 downto 0 )

Port

chan_rw_regs_in

chan_rw_regs_in in type_chan_rw_reg_array ( 3 downto 0 )

Port

common_drp_address_in

common_drp_address_in in std_logic_vector ( 7 downto 0 )

Port

common_drp_data_in

common_drp_data_in in std_logic_vector ( 15 downto 0 )

Port

common_drp_data_out

common_drp_data_out out std_logic_vector ( 15 downto 0 )

Port

common_drp_enable_in

common_drp_enable_in in std_logic

Port

common_drp_ready_out

common_drp_ready_out out std_logic

Port

common_drp_write_in

common_drp_write_in in std_logic

Port

common_ro_regs_out

common_ro_regs_out out type_common_ro_reg

Port

common_rw_regs_in

common_rw_regs_in in type_common_rw_reg

Port

drpclk_in

drpclk_in in std_logic

Port

ieee

ieee

Library

LOCAL_LHC_BUNCH_COUNT

LOCAL_LHC_BUNCH_COUNT integer

Generic

LOCAL_LHC_CLK_MULTIPLE

LOCAL_LHC_CLK_MULTIPLE integer := 4

Generic

numeric_std

numeric_std

Package

package_links

package_links

Package

package_types

package_types

Package

package_utilities

package_utilities

Package

qplllock

qplllock out std_logic

Port

refclk_in

refclk_in in std_logic

Port

rxclk_mon

rxclk_mon out std_logic_vector ( 3 downto 0 )

Port

rxdata_out

rxdata_out out type_32b_data_array ( 3 downto 0 )

Port

rxdatavalid_out

rxdatavalid_out out std_logic_vector ( 3 downto 0 )

Port

rxn_in

rxn_in in std_logic_vector ( 3 downto 0 )

Port

rxp_in

rxp_in in std_logic_vector ( 3 downto 0 )

Port

SIM_GTRESET_SPEEDUP

SIM_GTRESET_SPEEDUP string := " TRUE "

Generic

SIMULATION

SIMULATION integer := 0

Generic

std_logic_1164

std_logic_1164

Package

sysclk_in

sysclk_in in std_logic

Port

ttc_clk_in

ttc_clk_in in std_logic

Port

ttc_rst_in

ttc_rst_in in std_logic

Port

txclk_mon

txclk_mon out std_logic

Port

txdata_in

txdata_in in type_32b_data_array ( 3 downto 0 )

Port

txdatavalid_in

txdatavalid_in in std_logic_vector ( 3 downto 0 )

Port

txn_out

txn_out out std_logic_vector ( 3 downto 0 )

Port

txp_out

txp_out out std_logic_vector ( 3 downto 0 )

Port

unisim

unisim

Library

vcomponents

vcomponents

Package

X_LOC

X_LOC integer

Generic

Y_LOC

Y_LOC integer

Generic

---

The documentation for this class was generated from the following file:

• ipbus_lib/boards/kc705/base_fw/common/firmware/hdl/ext_align_gth_32b_10g_spartan.vhd