behave Architecture Reference

Processes
align_marker_proc	( ttc_clk_in )

Components
gtx_quad_wrapper_8b10bx32b	<Entity gtx_quad_wrapper_8b10bx32b>

Constants
BYTE_WIDTH	natural := 4
DATA_WIDTH	natural := 8 * BYTE_WIDTH
RAM18B_X_MULT	integer := 14
RAM18B_X_OFFSET	fset_array := ( 0 , 0 , 0 , 0 )
RAM18B_Y_MULT	integer := 20
RAM18B_Y_OFFSET	fset_array := ( 1 , 6 , 13 , 18 )

Types
info	array ( natural range <> ) of std_logic_vector ( DATA_WIDTH downto 0 )
offset_array	( 0 to 3 ) integer

Signals
txinfo_at_ttc_clk	info ( 3 downto 0 )
txinfo_at_link_clk	info ( 3 downto 0 )
txcomma_at_link_clk	std_logic_vector ( 3 downto 0 )
txdata_at_link_clk	type_32b_data_array ( 3 downto 0 )
txpad_at_link_clk	std_logic_vector ( 3 downto 0 )
txusrclk	std_logic_vector ( 3 downto 0 )
rxusrclk	std_logic_vector ( 3 downto 0 )
txusrrst	std_logic_vector ( 3 downto 0 )
rxusrrst	std_logic_vector ( 3 downto 0 )
txdata	type_32b_data_array ( 3 downto 0 )
rxdata	type_32b_data_array ( 3 downto 0 )
txcharisk	type_32b_charisk_array ( 3 downto 0 )
rxcharisk	type_32b_charisk_array ( 3 downto 0 )
loopback	type_loopback_array ( 3 downto 0 )
txpolarity	std_logic_vector ( 3 downto 0 )
rxpolarity	std_logic_vector ( 3 downto 0 )
rxchariscomma	type_32b_chariscomma_array ( 3 downto 0 )
rxpcommaalignen	std_logic_vector ( 3 downto 0 ) := " 1111 "
rxmcommaalignen	std_logic_vector ( 3 downto 0 ) := " 1111 "
rxbyteisaligned	std_logic_vector ( 3 downto 0 )
rxdata_int	type_32b_data_array ( 3 downto 0 )
rxdatavalid_int	std_logic_vector ( 3 downto 0 )
rxcdrlock	std_logic_vector ( 3 downto 0 )
txoutclk	std_logic_vector ( 3 downto 0 )
txdatavalid	std_logic_vector ( 3 downto 0 )
rxdatavalid	std_logic_vector ( 3 downto 0 )
rx_comma_det	std_logic_vector ( 3 downto 0 )
tx_fsm_reset	std_logic_vector ( 3 downto 0 )
rx_fsm_reset	std_logic_vector ( 3 downto 0 )
tx_fsm_reset_done	std_logic_vector ( 3 downto 0 )
rx_fsm_reset_done	std_logic_vector ( 3 downto 0 )
orbit_tag_enable	std_logic_vector ( 3 downto 0 )
align_disable	std_logic_vector ( 3 downto 0 )
buf_inc	std_logic_vector ( 3 downto 0 )
buf_dec	std_logic_vector ( 3 downto 0 )
rx_crc_checked_cnt	type_vector_of_stdlogicvec_x8 ( 3 downto 0 )
rx_crc_error_cnt	type_vector_of_stdlogicvec_x8 ( 3 downto 0 )
reset_crc_counters	std_logic_vector ( 3 downto 0 )
rx_trailer	type_vector_of_stdlogicvec_x32 ( 3 downto 0 )
tx_trailer	type_vector_of_stdlogicvec_x32 ( 3 downto 0 )
data_start	std_logic_vector ( 3 downto 0 )
divclk	std_logic_vector ( 4 downto 0 )
divclkout	std_logic_vector ( 4 downto 0 )
soft_reset	std_logic
soft_reset_sysclk	std_logic
qplllock_i	std_logic
quad_x_loc	std_logic
quad_y_loc	std_logic_vector ( 3 downto 0 )

Instantiations
div_ref	freq_ctr_div
tx_crc_insert	links_crc_tx
tx_clk_bridge	cdc_txdata_circular_buf
tx_kcode_insert	kcode_insert_commas_and_pad
sync_pulse_inst	async_pulse_sync
quad_wrapper_inst	gtx_quad_wrapper_8b10bx32b <Entity gtx_quad_wrapper_8b10bx32b>
rxdata_simple_cdc_buf_inst	rxdata_simple_cdc_buf
rx_crc	links_crc_rx

Member Function Documentation

align_marker_proc()

align_marker_proc

(

ttc_clk_in

)

Member Data Documentation

align_disable

align_disable std_logic_vector ( 3 downto 0 )

Signal

buf_dec

buf_dec std_logic_vector ( 3 downto 0 )

Signal

buf_inc

buf_inc std_logic_vector ( 3 downto 0 )

Signal

BYTE_WIDTH

BYTE_WIDTH natural := 4

Constant

data_start

data_start std_logic_vector ( 3 downto 0 )

Signal

DATA_WIDTH

DATA_WIDTH natural := 8 * BYTE_WIDTH

Constant

div_ref

div_ref freq_ctr_div

Instantiation

divclk

divclk std_logic_vector ( 4 downto 0 )

Signal

divclkout

divclkout std_logic_vector ( 4 downto 0 )

Signal

gtx_quad_wrapper_8b10bx32b

gtx_quad_wrapper_8b10bx32b

Component

info

info array ( natural range <> ) of std_logic_vector ( DATA_WIDTH downto 0 )

Type

loopback

loopback type_loopback_array ( 3 downto 0 )

Signal

offset_array

offset_array ( 0 to 3 ) integer

Type

orbit_tag_enable

orbit_tag_enable std_logic_vector ( 3 downto 0 )

Signal

qplllock_i

qplllock_i std_logic

Signal

quad_wrapper_inst

quad_wrapper_inst gtx_quad_wrapper_8b10bx32b

Instantiation

quad_x_loc

quad_x_loc std_logic

Signal

quad_y_loc

quad_y_loc std_logic_vector ( 3 downto 0 )

Signal

RAM18B_X_MULT

RAM18B_X_MULT integer := 14

Constant

RAM18B_X_OFFSET

RAM18B_X_OFFSET fset_array := ( 0 , 0 , 0 , 0 )

Constant

RAM18B_Y_MULT

RAM18B_Y_MULT integer := 20

Constant

RAM18B_Y_OFFSET

RAM18B_Y_OFFSET fset_array := ( 1 , 6 , 13 , 18 )

Constant

reset_crc_counters

reset_crc_counters std_logic_vector ( 3 downto 0 )

Signal

rx_comma_det

rx_comma_det std_logic_vector ( 3 downto 0 )

Signal

rx_crc

rx_crc links_crc_rx

Instantiation

rx_crc_checked_cnt

rx_crc_checked_cnt type_vector_of_stdlogicvec_x8 ( 3 downto 0 )

Signal

rx_crc_error_cnt

rx_crc_error_cnt type_vector_of_stdlogicvec_x8 ( 3 downto 0 )

Signal

rx_fsm_reset

rx_fsm_reset std_logic_vector ( 3 downto 0 )

Signal

rx_fsm_reset_done

rx_fsm_reset_done std_logic_vector ( 3 downto 0 )

Signal

rx_trailer

rx_trailer type_vector_of_stdlogicvec_x32 ( 3 downto 0 )

Signal

rxbyteisaligned

rxbyteisaligned std_logic_vector ( 3 downto 0 )

Signal

rxcdrlock

rxcdrlock std_logic_vector ( 3 downto 0 )

Signal

rxchariscomma

rxchariscomma type_32b_chariscomma_array ( 3 downto 0 )

Signal

rxcharisk

rxcharisk type_32b_charisk_array ( 3 downto 0 )

Signal

rxdata

rxdata type_32b_data_array ( 3 downto 0 )

Signal

rxdata_int

rxdata_int type_32b_data_array ( 3 downto 0 )

Signal

rxdata_simple_cdc_buf_inst

rxdata_simple_cdc_buf_inst rxdata_simple_cdc_buf

Instantiation

rxdatavalid

rxdatavalid std_logic_vector ( 3 downto 0 )

Signal

rxdatavalid_int

rxdatavalid_int std_logic_vector ( 3 downto 0 )

Signal

rxmcommaalignen

rxmcommaalignen std_logic_vector ( 3 downto 0 ) := " 1111 "

Signal

rxpcommaalignen

rxpcommaalignen std_logic_vector ( 3 downto 0 ) := " 1111 "

Signal

rxpolarity

rxpolarity std_logic_vector ( 3 downto 0 )

Signal

rxusrclk

rxusrclk std_logic_vector ( 3 downto 0 )

Signal

rxusrrst

rxusrrst std_logic_vector ( 3 downto 0 )

Signal

soft_reset

soft_reset std_logic

Signal

soft_reset_sysclk

soft_reset_sysclk std_logic

Signal

sync_pulse_inst

sync_pulse_inst async_pulse_sync

Instantiation

tx_clk_bridge

tx_clk_bridge cdc_txdata_circular_buf

Instantiation

tx_crc_insert

tx_crc_insert links_crc_tx

Instantiation

tx_fsm_reset

tx_fsm_reset std_logic_vector ( 3 downto 0 )

Signal

tx_fsm_reset_done

tx_fsm_reset_done std_logic_vector ( 3 downto 0 )

Signal

tx_kcode_insert

tx_kcode_insert kcode_insert_commas_and_pad

Instantiation

tx_trailer

tx_trailer type_vector_of_stdlogicvec_x32 ( 3 downto 0 )

Signal

txcharisk

txcharisk type_32b_charisk_array ( 3 downto 0 )

Signal

txcomma_at_link_clk

txcomma_at_link_clk std_logic_vector ( 3 downto 0 )

Signal

txdata

txdata type_32b_data_array ( 3 downto 0 )

Signal

txdata_at_link_clk

txdata_at_link_clk type_32b_data_array ( 3 downto 0 )

Signal

txdatavalid

txdatavalid std_logic_vector ( 3 downto 0 )

Signal

txinfo_at_link_clk

txinfo_at_link_clk info ( 3 downto 0 )

Signal

txinfo_at_ttc_clk

txinfo_at_ttc_clk info ( 3 downto 0 )

Signal

txoutclk

txoutclk std_logic_vector ( 3 downto 0 )

Signal

txpad_at_link_clk

txpad_at_link_clk std_logic_vector ( 3 downto 0 )

Signal

txpolarity

txpolarity std_logic_vector ( 3 downto 0 )

Signal

txusrclk

txusrclk std_logic_vector ( 3 downto 0 )

Signal

txusrrst

txusrrst std_logic_vector ( 3 downto 0 )

Signal

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The documentation for this class was generated from the following file:

• ipbus_lib/boards/kc705/base_fw/common/firmware/hdl/ext_align_gth_32b_10g_spartan.vhd