gtx_quad_wrapper_8b10bx32b Entity Reference

Inheritance diagram for gtx_quad_wrapper_8b10bx32b:

Entities
RTL	architecture

Libraries
ieee
UNISIM

Use Clauses
std_logic_1164
numeric_std
std_logic_unsigned
std_logic_misc
VCOMPONENTS
package_links
package_utilities

Generics
SIMULATION	integer := 0
SIM_GTRESET_SPEEDUP	string := " FALSE "
STABLE_CLOCK_PERIOD	integer := 32
LINE_RATE	real := 10 . 0
REFERENCE_CLOCK_RATE	real := 125 . 0
PRBS_MODE	string := " PRBS-7 "
X_LOC	integer := 0
Y_LOC	integer := 0

Ports
soft_reset_in	in std_logic
refclk_in	in std_logic
drpclk_in	in std_logic
sysclk_in	in std_logic
qplllock_out	out std_logic
rxusrclk_out	out std_logic_vector ( 3 downto 0 )
txusrclk_out	out std_logic_vector ( 3 downto 0 )
rxusrrst_out	out std_logic_vector ( 3 downto 0 )
txusrrst_out	out std_logic_vector ( 3 downto 0 )
rxn_in	in std_logic_vector ( 3 downto 0 )
rxp_in	in std_logic_vector ( 3 downto 0 )
txn_out	out std_logic_vector ( 3 downto 0 )
txp_out	out std_logic_vector ( 3 downto 0 )
tx_fsm_reset_in	in std_logic_vector ( 3 downto 0 )
rx_fsm_reset_in	in std_logic_vector ( 3 downto 0 )
tx_fsm_reset_done_out	out std_logic_vector ( 3 downto 0 )
rx_fsm_reset_done_out	out std_logic_vector ( 3 downto 0 )
rx_comma_det_out	out std_logic_vector ( 3 downto 0 )
txoutclk_out	out std_logic_vector ( 3 downto 0 )
loopback_in	in type_loopback_array ( 3 downto 0 )
txpolarity_in	in std_logic_vector ( 3 downto 0 )
rxpolarity_in	in std_logic_vector ( 3 downto 0 )
txdata_in	in type_32b_data_array ( 3 downto 0 )
txcharisk_in	in type_32b_charisk_array ( 3 downto 0 )
rxcdrlock_out	out std_logic_vector ( 3 downto 0 )
rxdata_out	out type_32b_data_array ( 3 downto 0 )
rxcharisk_out	out type_32b_charisk_array ( 3 downto 0 )
rxchariscomma_out	out type_32b_chariscomma_array ( 3 downto 0 )
rxbyteisaligned_out	out std_logic_vector ( 3 downto 0 )
rxpcommaalignen_in	in std_logic_vector ( 3 downto 0 )
rxmcommaalignen_in	in std_logic_vector ( 3 downto 0 )

Member Data Documentation

drpclk_in

drpclk_in in std_logic

Port

ieee

ieee

Library

LINE_RATE

LINE_RATE real := 10 . 0

Generic

loopback_in

loopback_in in type_loopback_array ( 3 downto 0 )

Port

numeric_std

numeric_std

Package

package_links

package_links

Package

package_utilities

package_utilities

Package

PRBS_MODE

PRBS_MODE string := " PRBS-7 "

Generic

qplllock_out

qplllock_out out std_logic

Port

refclk_in

refclk_in in std_logic

Port

REFERENCE_CLOCK_RATE

REFERENCE_CLOCK_RATE real := 125 . 0

Generic

rx_comma_det_out

rx_comma_det_out out std_logic_vector ( 3 downto 0 )

Port

rx_fsm_reset_done_out

rx_fsm_reset_done_out out std_logic_vector ( 3 downto 0 )

Port

rx_fsm_reset_in

rx_fsm_reset_in in std_logic_vector ( 3 downto 0 )

Port

rxbyteisaligned_out

rxbyteisaligned_out out std_logic_vector ( 3 downto 0 )

Port

rxcdrlock_out

rxcdrlock_out out std_logic_vector ( 3 downto 0 )

Port

rxchariscomma_out

rxchariscomma_out out type_32b_chariscomma_array ( 3 downto 0 )

Port

rxcharisk_out

rxcharisk_out out type_32b_charisk_array ( 3 downto 0 )

Port

rxdata_out

rxdata_out out type_32b_data_array ( 3 downto 0 )

Port

rxmcommaalignen_in

rxmcommaalignen_in in std_logic_vector ( 3 downto 0 )

Port

rxn_in

rxn_in in std_logic_vector ( 3 downto 0 )

Port

rxp_in

rxp_in in std_logic_vector ( 3 downto 0 )

Port

rxpcommaalignen_in

rxpcommaalignen_in in std_logic_vector ( 3 downto 0 )

Port

rxpolarity_in

rxpolarity_in in std_logic_vector ( 3 downto 0 )

Port

rxusrclk_out

rxusrclk_out out std_logic_vector ( 3 downto 0 )

Port

rxusrrst_out

rxusrrst_out out std_logic_vector ( 3 downto 0 )

Port

SIM_GTRESET_SPEEDUP

SIM_GTRESET_SPEEDUP string := " FALSE "

Generic

SIMULATION

SIMULATION integer := 0

Generic

soft_reset_in

soft_reset_in in std_logic

Port

STABLE_CLOCK_PERIOD

STABLE_CLOCK_PERIOD integer := 32

Generic

std_logic_1164

std_logic_1164

Package

std_logic_misc

std_logic_misc

Package

std_logic_unsigned

std_logic_unsigned

Package

sysclk_in

sysclk_in in std_logic

Port

tx_fsm_reset_done_out

tx_fsm_reset_done_out out std_logic_vector ( 3 downto 0 )

Port

tx_fsm_reset_in

tx_fsm_reset_in in std_logic_vector ( 3 downto 0 )

Port

txcharisk_in

txcharisk_in in type_32b_charisk_array ( 3 downto 0 )

Port

txdata_in

txdata_in in type_32b_data_array ( 3 downto 0 )

Port

txn_out

txn_out out std_logic_vector ( 3 downto 0 )

Port

txoutclk_out

txoutclk_out out std_logic_vector ( 3 downto 0 )

Port

txp_out

txp_out out std_logic_vector ( 3 downto 0 )

Port

txpolarity_in

txpolarity_in in std_logic_vector ( 3 downto 0 )

Port

txusrclk_out

txusrclk_out out std_logic_vector ( 3 downto 0 )

Port

txusrrst_out

txusrrst_out out std_logic_vector ( 3 downto 0 )

Port

UNISIM

UNISIM

Library

VCOMPONENTS

VCOMPONENTS

Package

X_LOC

X_LOC integer := 0

Generic

Y_LOC

Y_LOC integer := 0

Generic

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The documentation for this class was generated from the following file:

• ipbus_lib/boards/kc705/base_fw/common/firmware/hdl/gtx_quad_wrapper_8b10bx32b.vhd