My Project  v0.0.16
Constants | Signals | Attributes | Libraries | Use Clauses | Instantiations
RTL Architecture Reference

Libraries

generic_sync 
virtex_7_transceivers_common 
virtex_7_transceivers_gtx 

Use Clauses

definitions 
types 

Constants

DLY  time := 1 ns

Signals

txoutclk  std_logic_vector ( 3 downto 0 )
rxoutclk  std_logic_vector ( 3 downto 0 )
txusrclk  std_logic_vector ( 3 downto 0 )
rxusrclk  std_logic_vector ( 3 downto 0 )
txusrclk2  std_logic_vector ( 3 downto 0 )
rxusrclk2  std_logic_vector ( 3 downto 0 )
loopback_mode  array_gt_loopback ( 3 downto 0 )
rx_char_is_k  array_gt_k_data ( 3 downto 0 )
rx_data  array_gt_32b_data ( 3 downto 0 )
tx_char_is_k  array_gt_k_data ( 3 downto 0 )
tx_data  array_gt_32b_data ( 3 downto 0 )
tx_fsm_reset_done  std_logic_vector ( 3 downto 0 )
rx_fsm_reset_done  std_logic_vector ( 3 downto 0 )
tx_fsm_reset_n_done  std_logic_vector ( 3 downto 0 )
rx_fsm_reset_n_done  std_logic_vector ( 3 downto 0 )

Attributes

keep  string
keep  txusrclk : signal is " true "
keep  txusrclk2 : signal is " true "
keep  rxusrclk : signal is " true "
keep  rxusrclk2 : signal is " true "

Instantiations

rxusrrst_sync  async_pulse_sync
txusrrst_sync  async_pulse_sync
gt0_usrclk_source  usrclk_source
gtx_quad_i  gtx_quad

Member Data Documentation

◆ definitions

definitions
Package

◆ DLY

DLY time := 1 ns
Constant

◆ generic_sync

generic_sync
Library

◆ gt0_usrclk_source

gt0_usrclk_source usrclk_source
Instantiation

◆ gtx_quad_i

gtx_quad_i gtx_quad
Instantiation

◆ keep [1/5]

keep string
Attribute

◆ keep [2/5]

keep txusrclk : signal is " true "
Attribute

◆ keep [3/5]

keep txusrclk2 : signal is " true "
Attribute

◆ keep [4/5]

keep rxusrclk : signal is " true "
Attribute

◆ keep [5/5]

keep rxusrclk2 : signal is " true "
Attribute

◆ loopback_mode

loopback_mode array_gt_loopback ( 3 downto 0 )
Signal

◆ rx_char_is_k

rx_char_is_k array_gt_k_data ( 3 downto 0 )
Signal

◆ rx_data

rx_data array_gt_32b_data ( 3 downto 0 )
Signal

◆ rx_fsm_reset_done

rx_fsm_reset_done std_logic_vector ( 3 downto 0 )
Signal

◆ rx_fsm_reset_n_done

rx_fsm_reset_n_done std_logic_vector ( 3 downto 0 )
Signal

◆ rxoutclk

rxoutclk std_logic_vector ( 3 downto 0 )
Signal

◆ rxusrclk

rxusrclk std_logic_vector ( 3 downto 0 )
Signal

◆ rxusrclk2

rxusrclk2 std_logic_vector ( 3 downto 0 )
Signal

◆ rxusrrst_sync

rxusrrst_sync async_pulse_sync
Instantiation

◆ tx_char_is_k

tx_char_is_k array_gt_k_data ( 3 downto 0 )
Signal

◆ tx_data

tx_data array_gt_32b_data ( 3 downto 0 )
Signal

◆ tx_fsm_reset_done

tx_fsm_reset_done std_logic_vector ( 3 downto 0 )
Signal

◆ tx_fsm_reset_n_done

tx_fsm_reset_n_done std_logic_vector ( 3 downto 0 )
Signal

◆ txoutclk

txoutclk std_logic_vector ( 3 downto 0 )
Signal

◆ txusrclk

txusrclk std_logic_vector ( 3 downto 0 )
Signal

◆ txusrclk2

txusrclk2 std_logic_vector ( 3 downto 0 )
Signal

◆ txusrrst_sync

txusrrst_sync async_pulse_sync
Instantiation

◆ types

types
Package

◆ virtex_7_transceivers_common

◆ virtex_7_transceivers_gtx


The documentation for this class was generated from the following file: