My Project
v0.0.16
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Libraries | |
generic_sync | |
virtex_7_transceivers_common | |
virtex_7_transceivers_gtx |
Use Clauses | |
definitions | |
types |
Constants | |
DLY | time := 1 ns |
Signals | |
txoutclk | std_logic_vector ( 3 downto 0 ) |
rxoutclk | std_logic_vector ( 3 downto 0 ) |
txusrclk | std_logic_vector ( 3 downto 0 ) |
rxusrclk | std_logic_vector ( 3 downto 0 ) |
txusrclk2 | std_logic_vector ( 3 downto 0 ) |
rxusrclk2 | std_logic_vector ( 3 downto 0 ) |
loopback_mode | array_gt_loopback ( 3 downto 0 ) |
rx_char_is_k | array_gt_k_data ( 3 downto 0 ) |
rx_data | array_gt_32b_data ( 3 downto 0 ) |
tx_char_is_k | array_gt_k_data ( 3 downto 0 ) |
tx_data | array_gt_32b_data ( 3 downto 0 ) |
tx_fsm_reset_done | std_logic_vector ( 3 downto 0 ) |
rx_fsm_reset_done | std_logic_vector ( 3 downto 0 ) |
tx_fsm_reset_n_done | std_logic_vector ( 3 downto 0 ) |
rx_fsm_reset_n_done | std_logic_vector ( 3 downto 0 ) |
Attributes | |
keep | string |
keep | txusrclk : signal is " true " |
keep | txusrclk2 : signal is " true " |
keep | rxusrclk : signal is " true " |
keep | rxusrclk2 : signal is " true " |
Instantiations | |
rxusrrst_sync | async_pulse_sync |
txusrrst_sync | async_pulse_sync |
gt0_usrclk_source | usrclk_source |
gtx_quad_i | gtx_quad |
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